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| ics for communications isdn echocancellation circuit iec-q peb 2091 version 5.3 pef 2091 version 5.3 data sheet 01.99 ds 2
peb/f 2091 revision history: current version: 01.99 previous version: none page (in previous version) page (in current version) subjects (major changes since last revision) edition 1.99 published by siemens ag, hl sc, balanstra?e 73, 81541 mnchen ? siemens ag 1999. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be en- dangered. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens companies and representatives worldwide: see our webpage at http://www.siemens.de/semicon- ductor/communication. abm ? , aop ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, digitape ? , epic ? -1, epic ? -s, elic ? , falc ? 54, falc ? 56, falc ? -e1, falc ? -lh, idec ? , iom ? , iom ? -1, iom ? -2, ipat ? -2, isac ? -p, isac ? -s, isac ? -s te, isac ? -p te, itac ? , iwe ? , musac ? -a, octat ? -p, quat ? -s, sicat ? , sicofi ? , sicofi ? -2, sicofi ? -4, sicofi ? -4c, slicofi ? are registered trademarks of siemens ag. ace ? , asm ? , asp ? , potswire ? , quadfalc ? , scout ? are trademarks of siemens ag. purchase of siemens i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c-system provided the system conforms to the i 2 c specifications defined by philips. copyright philips 1983. all brand or product names, hardware or software names are trademarks or registered trademarks of their respective companies or organizations. peb 2091 pef 2091 table of contents page semiconductor group 3 data sheet 01.99 preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.2 ordering codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.3 logic symbol for p mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.4 logic symbol for stand-alone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.5.1 pcm 2 systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.5.2 pcm 4 with fax/modem features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.5.3 repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.5.4 wireless local loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.5.5 te applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.5.6 dual mode u and s terminals and pc cards . . . . . . . . . . . . . . . . . . . . .27 1.5.7 nt-pbx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 1.5.8 lt application and access network . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 1.5.9 nt1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.1.1 p-lcc-44 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.1.2 t-qfp-64 and m-qfp-64 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2.2.1 pin definition in stand-alone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 2.2.1.1 mode selection pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 2.2.1.2 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.2.1.3 iom ? -2 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2.2.1.4 iom ? -2 control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2.2.1.5 u-interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 2.2.1.6 power controller pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 2.2.1.7 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 2.2.1.8 miscellaneous function pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.2.1.9 test pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.2.2 pin definition in microprocessor mode . . . . . . . . . . . . . . . . . . . . . . . . . .40 2.2.2.1 mode selection pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 2.2.2.2 data, address and p selection pins . . . . . . . . . . . . . . . . . . . . . . . . .40 2.2.2.3 p control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 2.2.2.4 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 2.2.2.5 iom ? -2 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 2.2.2.6 u-interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 2.2.2.7 power controller pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 2.2.2.8 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 peb 2091 pef 2091 table of contents page semiconductor group 4 data sheet 01.99 2.2.2.9 miscellaneous function pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 2.2.2.10 test pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 2.3 microprocessor bus interface (overview) . . . . . . . . . . . . . . . . . . . . . . . . . .48 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 3.1 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 3.2 setting operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 3.2.1 basic operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 3.2.2 test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 3.2.3 dout driver modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 3.2.4 iom ? -2 enable/disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 3.2.5 eoc auto/transparent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.2.6 monitor procedure time-out (mto) . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.2.7 setting iom ? -2 bit clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 3.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 3.4 transceiver core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 3.4.1 system interface unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 3.4.2 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 3.4.3 line interface unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 3.5 u-interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 3.5.1 output and input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 3.5.2 u -frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 3.6 iom ? -2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 3.6.1 iom ? -2 frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 3.6.1.1 multiplexed timing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 3.6.1.2 plain timing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 3.6.1.3 terminal timing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 3.6.2 iom ? -2 command / indication channels . . . . . . . . . . . . . . . . . . . . . . . .75 3.6.2.1 active c/i channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 3.6.2.2 c/i channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 3.6.3 iom ? -2 monitor channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 3.6.3.1 active monitor channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 3.6.3.2 monitor channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 3.6.3.3 monitor procedure time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 3.6.4 activation/deactivation of iom ? -2 clocks . . . . . . . . . . . . . . . . . . . . . . . .82 3.7 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 3.7.1 lt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 3.7.2 nt and te mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 3.7.3 nt-pbx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 3.7.4 repeater modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 3.7.4.1 nt repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 3.7.4.2 lt repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 3.7.5 cot-512 and cot-1536 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 peb 2091 pef 2091 table of contents page semiconductor group 5 data sheet 01.99 3.7.6 microprocessor clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 3.8 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 3.9 s/g bit and bac bit control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 3.10 power controller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 3.11 power status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 3.12 undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 3.13 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 3.14 power on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 3.15 reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 3.16 test block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 4 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 4.1 microprocessor access to iom ? -2 channels . . . . . . . . . . . . . . . . . . . . . . .97 4.1.1 b-channel access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 4.1.2 d-channel access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 4.1.3 c/i channel access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 4.1.4 monitor channel access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 4.1.4.1 monitor channel protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 4.2 access to u-interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 4.2.1 access to data channels of u-interface . . . . . . . . . . . . . . . . . . . . . . . .108 4.2.2 access to eoc of u-interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 4.2.3 access to the single bits of u-interface . . . . . . . . . . . . . . . . . . . . . . . .115 4.2.3.1 single bits transmission on u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 4.2.3.2 single bits reception from u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 4.2.4 setting superframe marker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 4.3 layer 1 activation and deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 4.3.1 complete activation initiated by lt . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 4.3.2 activation with act-bit status ignored by the exchange side . . . . . . .127 4.3.3 complete activation initiated by te . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 4.3.4 complete deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 4.3.5 partial activation (u only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 4.3.6 activation initiated by lt with u active . . . . . . . . . . . . . . . . . . . . . . . . .131 4.3.7 activation initiated by te with u active . . . . . . . . . . . . . . . . . . . . . . . . .132 4.3.8 deactivating s/t-interface only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 4.3.9 activation initiated by lt with repeater . . . . . . . . . . . . . . . . . . . . . . . .135 4.3.10 activation initiated by te with repeater . . . . . . . . . . . . . . . . . . . . . . . .136 4.3.11 loss of synchronization / signal at repeater . . . . . . . . . . . . . . . . . . . .137 4.3.12 deactivation with repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 4.3.13 activation attempt initiated by nt in nt-auto activation mode . . . . . . .142 4.3.14 activation in the p-nt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 4.3.15 upstream wake-up indication in the lt repeater mode . . . . . . . . . . .143 4.4 state machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 4.4.1 state machine notation rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 peb 2091 pef 2091 table of contents page semiconductor group 6 data sheet 01.99 4.4.2 state machine in lt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 4.4.2.1 lt modes state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 4.4.2.2 transition criteria in lt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 4.4.2.3 output signals and indications in lt modes . . . . . . . . . . . . . . . . . . .154 4.4.2.4 lt states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 4.4.3 state machine in nt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 4.4.3.1 nt modes state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 4.4.3.2 transition criteria in nt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 4.4.3.3 output signals and indications in nt modes . . . . . . . . . . . . . . . . . . .167 4.4.3.4 nt states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 4.4.4 state machine in repeater modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 4.5 monitoring transmission quality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 4.5.1 block error counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 4.5.1.1 nebe counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 4.5.1.2 febe counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 4.5.1.3 testing block error counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 4.6 chip internal test options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 4.6.1 self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 4.6.2 receiver coefficient values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 4.7 test loop-backs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 4.7.1 analog loop-back (no. 1/no. 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 4.7.2 partial and complete loop-back (no. 2) . . . . . . . . . . . . . . . . . . . . . . . .188 4.7.2.1 complete loop-back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 4.7.2.2 single-channel loop-backs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 4.7.2.3 repeater loop-back (no. 1a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 4.7.2.4 codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 4.8 chip identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 4.9 access to power status pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 4.9.1 monitoring primary and secondary nt power supply . . . . . . . . . . . . .194 4.9.2 monitoring remote power feed circuit in lt modes . . . . . . . . . . . . . .194 4.9.3 monitoring power feed current in lt modes . . . . . . . . . . . . . . . . . . . .194 4.9.4 access to pin diss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 4.10 access to power controller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 4.10.1 data port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 4.10.2 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 4.11 s/g bit and bac bit operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 4.11.1 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 4.11.2 indication of s/g bit status on pin sg . . . . . . . . . . . . . . . . . . . . . . . . .205 5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 5.1 interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 5.1.1 monitor-channel interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 5.2 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210 peb 2091 pef 2091 table of contents page semiconductor group 7 data sheet 01.99 5.2.1 ista-register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210 5.2.2 mask-register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 5.2.3 stcr-register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212 5.2.4 adf2-register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 5.2.5 mosr-register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 5.2.6 mocr-register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 5.2.7 ciru-register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217 5.2.8 ciwu-register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217 5.2.9 ciri-register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 5.2.10 ciwi-register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 5.2.11 adf-register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 5.2.12 swst-register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 5.2.13 b-channel access registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 5.2.14 d-channel access registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 5.2.15 monitor-channel access registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 6 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 6.1 c/i channel codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 6.2 monitor channel codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 6.2.1 mon-0 codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 6.2.2 mon-1 codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 6.2.3 mon-2 codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228 6.2.4 mon-8 codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228 6.3 predefined eoc codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 6.4 example for c/i channel programming . . . . . . . . . . . . . . . . . . . . . . . . . . .232 6.5 example for monitor channel programming . . . . . . . . . . . . . . . . . . . . . . .233 6.6 example for programming power controller interface . . . . . . . . . . . . . . .235 6.7 examples for activating test loop-backs . . . . . . . . . . . . . . . . . . . . . . . . .236 6.7.1 examples for analog loop-back control . . . . . . . . . . . . . . . . . . . . . . . .236 6.7.2 examples for complete loop-back #2 control . . . . . . . . . . . . . . . . . . .237 6.7.3 examples for single channel loop-back #2 control . . . . . . . . . . . . . . .239 6.8 examples for activation and deactivation control codes . . . . . . . . . . . . .241 6.8.1 complete activation initiated by lt . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 6.8.2 complete activation initiated by te . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 6.8.3 activation with act-bit status ignored by exchange side . . . . . . . . . .243 6.8.4 complete deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 6.8.5 partial activation (u only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 6.8.6 complete activation initiated by lt with u active . . . . . . . . . . . . . . . . .244 6.8.7 complete activation initiated by te with u active . . . . . . . . . . . . . . . . .245 6.8.8 deactivating s/t-interface only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246 6.8.9 activation initiated by lt with repeater . . . . . . . . . . . . . . . . . . . . . . . .246 6.8.10 activation initiated by te with repeater . . . . . . . . . . . . . . . . . . . . . . . .247 6.8.11 deactivation by repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 peb 2091 pef 2091 table of contents page semiconductor group 8 data sheet 01.99 7 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 7.1 external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 7.1.1 power supply blocking recommendation . . . . . . . . . . . . . . . . . . . . . . .249 7.1.2 u-interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 7.1.3 oscillator circuit and crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 7.2 applications with epic ? on the line card (pbx) . . . . . . . . . . . . . . . . . . .253 7.3 hints for repeater applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 7.3.1 eoc addressing management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 7.3.2 single bits handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 7.4 set-ups for test modes and system measurements . . . . . . . . . . . . . . . . .259 7.4.1 tests in send single pulses mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 7.4.2 tests in data-through mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 7.4.3 tests in master-reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 8 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 8.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .262 8.2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 8.3 line overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 8.4 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265 8.5 analog characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 8.6 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268 8.7 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 8.7.1 microprocessor interface timing in parallel mode . . . . . . . . . . . . . . . . .269 8.7.1.1 siemens/intel bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270 8.7.1.2 motorola bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 8.7.1.3 timing values of the p interface in parallel mode . . . . . . . . . . . . . .272 8.7.2 serial microprocessor interface timing . . . . . . . . . . . . . . . . . . . . . . . . .273 8.7.3 iom ? -2 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274 8.7.4 power controller interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277 8.7.4.1 data port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277 8.7.4.2 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 8.7.5 undervoltage detection timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280 8.7.6 master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 8.7.6.1 lt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 8.7.6.2 nt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 8.7.7 timing properties of cls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284 8.7.8 timing properties of pin sg in te mode . . . . . . . . . . . . . . . . . . . . . . . .286 9 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 10 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 11 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 peb 2091 pef 2091 table of contents page semiconductor group 9 data sheet 01.99 appendix a basic standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 appendix b comment on activation in p-nt modes . . . . . . . . . . . . . . . . . . . . . .298 peb 2091 pef 2091 list of figures page semiconductor group 10 data sheet 01.99 figure 1 logic symbol for p mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 2 logic symbol for stand-alone mode . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 3 cot application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 4 rt application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 5 pcm 4 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 6 architecture of repeater application . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 7 architecture of the wireless local loop base station . . . . . . . . . . . . . .26 figure 8 te application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 9 dual mode pc adapter card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 10 nt-pbx application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 11 lt and access network applications. . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 12 nt1 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 13 pin configuration for p-lcc-44 package (top view) . . . . . . . . . . . . . . .31 figure 14 pin configuration for m-qfp-64 and t-qfp-64 packages (top view) . .32 figure 15 stand-alone mode (left) and p mode (right) . . . . . . . . . . . . . . . . . . . .50 figure 16 device architecture in p mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 figure 17 device architecture in stand-alone mode . . . . . . . . . . . . . . . . . . . . . . .59 figure 18 u transceiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 19 scrambler / descrambler algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . .63 figure 20 dac-output for a single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 figure 21 u-superframe structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 figure 22 u-basic frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 figure 23 iom ? -2 clocks and data lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 figure 24 basic channel structure of iom ? -2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 figure 25 multiplexed frame structure of the iom ? -2 interface . . . . . . . . . . . . . .72 figure 26 plain frame structure of the iom ? -2 interface . . . . . . . . . . . . . . . . . . .73 figure 27 terminal frame structure of the iom ? -2 interface . . . . . . . . . . . . . . . .74 figure 28 handshake protocol with a 2-byte monitor message/response . . . . . .78 figure 29 abortion of monitor channel transmission . . . . . . . . . . . . . . . . . . . . . .79 figure 30 monitor access with mto enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 figure 31 deactivation of the iom ? -2 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 figure 32 clock generation for lt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 figure 33 clock in nt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 figure 33 clocks in te mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 figure 34 clock generation in nt-pbx mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 figure 35 clock generation in repeater mode . . . . . . . . . . . . . . . . . . . . . . . . . . .87 figure 36 clocks in cot-512 mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 figure 36 clocks in cot-1536 mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 figure 37 uvd control of pin rst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 figure 38 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 figure 39 access to iom ? -2 channels (p mode) . . . . . . . . . . . . . . . . . . . . . . . .97 figure 40 procedure for the d-channel processing . . . . . . . . . . . . . . . . . . . . . . .99 peb 2091 pef 2091 list of figures page semiconductor group 11 data sheet 01.99 figure 41 c/i channel access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 figure 42 monitor channel access directions . . . . . . . . . . . . . . . . . . . . . . . . . . .102 figure 43 monitor channel protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 figure 44 channels of access to u-interface (transmitter) . . . . . . . . . . . . . . . . .106 figure 45 channels of access to u-interface (receiver) . . . . . . . . . . . . . . . . . . .107 figure 46 access to data transmission on u . . . . . . . . . . . . . . . . . . . . . . . . . . .108 figure 47 access to data received from u . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 figure 48 access to eoc transmission on u . . . . . . . . . . . . . . . . . . . . . . . . . . .111 figure 49 access to eoc received from u . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 figure 50 eoc-procedure in auto and transparent mode . . . . . . . . . . . . . . . . .114 figure 51 access to single bits transmission on u . . . . . . . . . . . . . . . . . . . . . .115 figure 52 access to single bits received from u . . . . . . . . . . . . . . . . . . . . . . . .120 figure 53 complete activation initiated by lt . . . . . . . . . . . . . . . . . . . . . . . . . . .126 figure 54 activation with act-bit status ignored by the exchange . . . . . . . . . .127 figure 55 complete activation initiated by te . . . . . . . . . . . . . . . . . . . . . . . . . . .128 figure 56 complete deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 figure 57 u only activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 figure 58 lt initiated activation with u-interface active . . . . . . . . . . . . . . . . . . .131 figure 59 te activation with u active and exchange control (case 1) . . . . . . . .132 figure 60 te activation with u active and no exchange control (case 2) . . . . .133 figure 61 deactivation of s/t only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 figure 62 activation with repeater initiated by lt. . . . . . . . . . . . . . . . . . . . . . . .135 figure 63 activation with repeater initiated by te . . . . . . . . . . . . . . . . . . . . . . .136 figure 64 loss of synchronization at repeater (lt side) . . . . . . . . . . . . . . . . . .137 figure 65 loss of signal at repeater (lt side) . . . . . . . . . . . . . . . . . . . . . . . . . .138 figure 66 loss of synchronization at repeater (nt side) . . . . . . . . . . . . . . . . . .139 figure 67 loss of signal at repeater (nt side) . . . . . . . . . . . . . . . . . . . . . . . . . .140 figure 68 deactivation with repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 figure 69 din control via ciwu:spu in nt p mode. . . . . . . . . . . . . . . . . . . . .142 figure 70 wake up indication in repeater power down . . . . . . . . . . . . . . . . . . .143 figure 71 state diagram notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 figure 72 state transition diagram in lt modes . . . . . . . . . . . . . . . . . . . . . . . .147 figure 73 state transition diagram in nt, te and nt-pbx modes . . . . . . . . . .161 figure 74 state transition diagram in nt-auto activation mode . . . . . . . . . . . .162 figure 75 state transition diagram lt-repeater mode . . . . . . . . . . . . . . . . . . .174 figure 76 state transition diagram nt-repeater mode . . . . . . . . . . . . . . . . . . .175 figure 77 relationship between crc and febe bits and superframe number .177 figure 78 block error counter test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 figure 79 crc violation indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 figure 80 test loop-backs supported by the iec-q. . . . . . . . . . . . . . . . . . . . . .187 figure 81 complete loop-back options in nt modes. . . . . . . . . . . . . . . . . . . . .189 figure 82 closing loop-back #1a in a multi-repeater system . . . . . . . . . . . . . .191 peb 2091 pef 2091 list of figures page semiconductor group 12 data sheet 01.99 figure 83 serial data port of pin ps2 in lt modes . . . . . . . . . . . . . . . . . . . . . . .195 figure 84 sampling of interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 figure 85 state machine notation for s/g bit control . . . . . . . . . . . . . . . . . . . . .200 figure 86 state machine for s/g bit control (part 1) . . . . . . . . . . . . . . . . . . . . . .201 figure 87 state machine for s/g bit control (part 2) . . . . . . . . . . . . . . . . . . . . . .202 figure 88 state machine for s/g bit control (part 3) . . . . . . . . . . . . . . . . . . . . . .203 figure 89 s/g bit status on pin s/g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 figure 91 example: c/i-channel use (all data values hexadecimal) . . . . . . . . . .232 figure 92 power supply blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 figure 93 u-interface hybrid circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 figure 94 crystal oscillator or external clock source . . . . . . . . . . . . . . . . . . . . .252 figure 95 d-channel request by the terminal . . . . . . . . . . . . . . . . . . . . . . . . . .256 figure 96 eoc-handling in repeater applications . . . . . . . . . . . . . . . . . . . . . . .257 figure 97 maintenance bit handling in repeaters (example) . . . . . . . . . . . . . . .258 figure 98 total power measurement set-up. . . . . . . . . . . . . . . . . . . . . . . . . . . .260 figure 99 maximum sinusoidal ripple on supply voltage . . . . . . . . . . . . . . . .263 figure 100 test condition for maximum input current . . . . . . . . . . . . . . . . . . . . .264 figure 101 u transceiver input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 figure 102 pulse mask for a single positive pulse . . . . . . . . . . . . . . . . . . . . . . . .267 figure 103 input/output wave form for ac tests . . . . . . . . . . . . . . . . . . . . . . . . .269 figure 104 siemens/intel read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270 figure 105 siemens/intel write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270 figure 106 siemens/intel multiplexed address timing . . . . . . . . . . . . . . . . . . . . .270 figure 107 siemens/intel non-multiplexed address timing . . . . . . . . . . . . . . . . .271 figure 108 motorola read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 figure 109 motorola write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 figure 110 motorola non-multiplexed address timing . . . . . . . . . . . . . . . . . . . . .272 figure 111 serial p interface mode write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273 figure 112 serial p interface mode read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273 figure 113 iom ? -2 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274 figure 114 iom ? -2 timing of iom ? -2 interface (detail) . . . . . . . . . . . . . . . . . . . .275 figure 115 dynamic characteristics of power controller write access. . . . . . . . .277 figure 116 dynamic characteristics of power controller read access . . . . . . . .278 figure 117 dynamic characteristics of interrupt . . . . . . . . . . . . . . . . . . . . . . . . . .279 figure 118 uvd timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280 figure 119 clock requirements in lt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 figure 120 dynamic characteristics of the duty cycle . . . . . . . . . . . . . . . . . . . . .282 figure 121 maximum sinusoidal input jitter of master clock 15.36 mhz . . . . . . .282 figure 122 clock requirements in nt-pbx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284 figure 123 dynamic characteristics of cls . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284 figure 124 dynamic characteristics of pin sg . . . . . . . . . . . . . . . . . . . . . . . . . . .286 figure 125 package outline for p-lcc-44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 peb 2091 pef 2091 list of figures page semiconductor group 13 data sheet 01.99 figure 126 package outline for m-qfp-64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288 figure 127 package outline for t-qfp-64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 peb 2091 pef 2091 list of tables page semiconductor group 14 data sheet 01.99 table 1 microprocessor bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 2 setting modes of operation (stand-alone and p mode) . . . . . . . . . . 51 table 3 setting iom ? -2 channel assignment. . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 4 setting test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 5 setting dout driver in stand-alone mode . . . . . . . . . . . . . . . . . . . . . 53 table 6 setting dout driver in p mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 7 setting iom ? -2 clock enable/disable mode . . . . . . . . . . . . . . . . . . . . 55 table 8 setting eoc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 9 setting mto mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 10 u-frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 11 general monitor channel structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 12 microprocessor interface modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 13 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 14 b1/b2-channel data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 15 d-channel data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 16 monitor transmit bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 17 monitor receive bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 18 content of mon-0 message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 19 predefined eoc messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 20 content of mon-2 message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 21 single bits control in nt modes (upstream) . . . . . . . . . . . . . . . . . . . 116 table 22 function of the predefined sb in nt modes . . . . . . . . . . . . . . . . . . . 117 table 23 single bits control in lt modes (downstream) . . . . . . . . . . . . . . . . . 119 table 24 function of the predefined sb in lt modes . . . . . . . . . . . . . . . . . . . 119 table 25 format of mon-8-messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 26 setting filtering method for m4 bits . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 27 setting filtering method for additional overhead bits . . . . . . . . . . . . 123 table 28 u-interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 29 timers for lt state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 30 timers for nt state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 31 internal coefficient addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 32 mon-8 and c/i-commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 33 s/g bit control overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 table 34 state machine input signals for s/g control . . . . . . . . . . . . . . . . . . . 204 table 35 state machine output signals for s/g control . . . . . . . . . . . . . . . . . 204 table 36 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 table 37 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 table 38 command / indicate codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 table 39 c/i-abbreviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 table 40 format of mon-0-commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 table 41 predefined mon-0 commands and indications . . . . . . . . . . . . . . . . 226 table 42 format of mon-1 messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 peb 2091 pef 2091 list of tables page semiconductor group 15 data sheet 01.99 table 43 mon-1 s/q-channel commands and indications . . . . . . . . . . . . . . . 227 table 44 mon-1 m-bit commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 table 45 format of mon-2-messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 table 46 format of mon-8-messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 table 47 mon-8-local function commands . . . . . . . . . . . . . . . . . . . . . . . . . . 229 table 48 supported eoc-commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 table 49 control structure of the s/g bit and of the d-channel . . . . . . . . . . . 254 table 50 timing characteristics (serial p interface mode) . . . . . . . . . . . . . . . 274 table 51 iom ? -2 dynamic input characteristics . . . . . . . . . . . . . . . . . . . . . . . 275 table 52 iom ? -2 dynamic output characteristics . . . . . . . . . . . . . . . . . . . . . . 276 table 53 power controller interface dynamic characteristics . . . . . . . . . . . . . 278 table 54 dynamic characteristics of interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 279 table 55 timing parameters of uvd function . . . . . . . . . . . . . . . . . . . . . . . . . 280 table 56 duty ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 table 60 output characteristics of pin s/g . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 peb 2091 pef 2091 semiconductor group 16 data sheet 01.99 preface the isdn echocancellation circuit for the 2b1q line code (iec-q) is a u-interface transceiver for level 1 basic access subscriber lines covering a wide range of applications related to this function. this data sheet describes the properties of the iec-q needed for understanding its external connections, architecture and functions, and for designing circuits using this device. organization of this document this document follows a top-down approach in describing the iec-q and its features. it is application oriented, designed to maximize customers effectivity in designing and debugging their boards. numerous examples of programming code and application hints are included. an index is included. it consists of 11 chapters and an appendix. ? chapter 1, overview describes the system related view of the device, i.e. features, system integration and typical applications. ? chapter 2, pin descriptions gives a detailed description of the device pins, their functions and their physical location for the different packages available. ? chapter 3, functional description provides a high level block diagram of the iec-q, describes setting its operational modes and gives an overview of the device architecture. all users interfaces are described in detail. interaction between these interfaces, however, is not in the scope of this chapter. ? chapter 4, operational description describes access means to the iec-q features and the resulting device behavior in all relevant operational modes. interaction between the different interfaces is described. ? chapter 5, register description provides a detailed description of the registers used in the microprocessor mode. ? chapter 6, programming gives an overview of important programming codes and provides numerous practical programming examples. peb 2091 pef 2091 semiconductor group 17 data sheet 01.99 ? chapter 7, application hints describes the external circuitry needed and gives useful hints for some applications. ? chapter 8, electrical characteristics specifies the statical and dynamical characteristics of the devices inputs and outputs, its maximum rating, power supply, power consumption and other important electrical characteristics. ? chapter 9, package outlines outlines the geometry of the three packages available. ? chapter 10, glossary. ? chapter 11, index. ? appendix a listing of basic standards and some remarks are included. peb 2091 pef 2091 overview semiconductor group 18 data sheet 01.99 1 overview version 5.3 of the peb/f 2091 (iec-q), is an optimized version of the iec-q, which features all functions needed for building basic rate digital subscriber line systems. it complies to all international and all important national standards (e.g. itu, ansi, etsi, cnet, bt). the iec-q holds the bellcore approval for "layer 1 isdn basic access digital subscriber line transceivers", including all objectives, and it is the de facto industrial standard for these applications. the iec-q is one building stone of the siemens u transceiver product family for the 2b1q line code, which is divided into three groups of products ? iec afe/dfe-q (peb 24902 / peb 24911) ? ntc-q and intc-q (peb 8091/peb8191) ? iec-q the iec afe/dfe kit is optimized to interface four metallic lines in the lt allowing cost effective design for line cards in the switch and in wireless local loop applications (lt). the ntc-q is a one chip solution for nt1 systems offering all needed level 1 functions for this application. the functions of the ntc-q are a subset of these of the intc-q, which offers additional features for comfortable and cost effective implementation of intelligent nts. the iec-q provides numerous features supporting comfortable and cost effective implementation of ? digital added main line (daml) pcm-2 and pcm-4 applications ? repeater applications ? wireless local loop applications (base station) ? te applications ? nt-pbx and access network applications from the technical point of view, it can also be used in standard nt and lt applications. the iec-q allows access to the u-interface via iom ? -2 interface, microprocessor interface or a combination of both. it also provides means to support monitoring transmission quality, monitoring power supply, activation and deactivation procedures for special modes, performing maintenance tests and other features. version 5.3 is available in three different packages and in two operational temperature ranges. it offers ? new features to support applications gaining increasing importance in the marketplace, e.g. wireless local loop, repeaters, dual mode s and u terminals and pc cards, ? improved electrical behavior and functions (power consumption, esd immunity, dynamic characteristics of the microprocessor interface) as well as ? full compatibility to previous iec-q versions p-lcc-44 m-qfp-64 t-qfp-64 isdn echocancellation circuit iec-q peb 2091 pef 2091 semiconductor group 19 data sheet 01.99 version 5.3 cmos 1.1 features ? isdn u transceiver with iom ? -2 and microprocessor interface control ? pin and functionally compatible to all previous peb 2091 versions ? perfectly suited to all lt, nt, te, daml, repeater, nt-pbx and wireless local loop applications. ? u-interface (2b1q) conforms to all relevant international standardization norms (e.g. itu, ansi, etsi) and all important national norms (e.g. cnet, bt), including all optional transmission requirements with sufficient margin. ? application optimized dsp with adaptive echo cancellation and equalization, automatic polarity adaption, clock recovery, automatic gain control and build-in wake-up function. ?iom ? -2 interface for connection of e.g. epic ? , elic ? , idec ? , sbc-x, icc, sicofi ? -2/4, sicofi ? -2/4te, isac ? -s, arcofi ? , itac ? , hscx-te, isar, ipac, 3pac ? automatic maintenance control features ? multipurpose controller interface in stand-alone mode ? single 5 volt power supply ? low power cmos technology with power down mode ? available in three packages: p-lcc-44, m-qfp-64 and t-qfp-64 ? available in the extended temperature range in p mode ? parallel or serial microprocessor interface ? wake up function in nt mode without iom ? -2 ? undervoltage detection circuit ? watchdog peb 2091 pef 2091 overview semiconductor group 20 data sheet 01.99 ? p access to all data and control channels of the iom ? -2 interface ? adjustable microcontroller clock source between 0.96mhz and 7.68mhz ? selection between bit clock (bcl) and data clock (dcl) ? supports synchronization of base stations in wireless local loop applications ? supports d-channel arbitration with elic ? linecard (e.g. pbx) 1.2 ordering codes type ordering code package peb 2091 n v5.3 q67236-h1078 p-lcc-44 pef 2091 n v5.3 q67236-h1069 p-lcc-44 pef 2091 h v5.3 q67237-h1079 m-qfp-64 pef 2091 f v5.3 q67237-h1077 t-qfp-64 peb 2091 pef 2091 overview semiconductor group 21 data sheet 01.99 1.3 logic symbol for p mode figure 1 logic symbol for p mode peb 2091 iec-q p mode pmode res gnd vdd xin xout aout bout ain bin ps1 ps2 rst smode mclk int cs wr rd ale ad0-ad7 dout din dcl* fsc* cls iom ? -2 interface u interface power supply control 15.36 mhz **) +5v 0v reset +5v clock parallel / serial siemens or motorola p interface *) fsc and dcl are inputs in the iom ? -2 slave mode and outputs from the iom ? -2 master mode **) crystal or external clock on xin peb 2091 pef 2091 overview semiconductor group 22 data sheet 01.99 1.4 logic symbol for stand-alone mode figure 2 logic symbol for stand-alone mode peb 2091 iec-q stand alone mode pmode xin xout aout bout ain bin ps1 ps2 int pcrd pcwr pca0- 1 pcd0-2 cls u interface power supply control 0v clock power controller interface *) fsc and dcl are inputs in the iom ? -2 slave mode and outputs from the iom ? -2 master mode **) crystal or external clock on xin res gnd vdd +5v 0v tsp burst ts0-2 mode selection dout din dcl* fsc* iom-2 interface dod mto iom ? -2 control diss auto lt 15.36 mhz **) peb 2091 pef 2091 overview semiconductor group 23 data sheet 01.99 1.5 system integration the peb/f 2091 can be combined with a variety of other devices to fit in numerous applications. some of the typical 1) layer-1 applications are sketched below. 1.5.1 pcm 2 systems figure 3 cot application figure 4 rt application 1) typical applications are not necessarily covered by system tests or reference designs performed by siemens, and they may be subject to future changes a/b iec-q peb/f 2091 u interface a/b sicofi ? -2 c peb 2266 v1.4 iom ? -2 p sicofi ? -2 c peb 2266 v1.4 slic iec-q peb/f 2091 u interface iom ? -2 slic p peb 2091 pef 2091 overview semiconductor group 24 data sheet 01.99 1.5.2 pcm 4 with fax/modem features figure 5 pcm 4 application 1.5.3 repeater the iec-q offers several special features to allow simple and cost effective design of repeaters. beside the microprocessor interface, free programming of maintenance bits and special state machines for activation and deactivation control, the following three features are of interest ? a wake-up tone from downstream is indicated directly on dout. no special circuit for wake tone detection is needed. see "upstream wake-up indication in the lt repeater mode", page 143. ? a master clock is delivered on pin cls in the nt repeater mode. this allows reducing power consumption to a minimum in power down. furthermore, pll architecture can be simplified. see "clocks", page 45. ? the undervoltage detection function can be used to detect power supply level drops on the board and reduce external reset circuitry. refer to "undervoltage detection", page 92. sicofi ? -4 c peb 2466 iec-q peb/f 2091 u interface iom ? -2 a/b p adpcm peb 7274 a/b a/b a/b isar psb 7110 parallel interface serial interface cot or te mode peb 2091 pef 2091 overview semiconductor group 25 data sheet 01.99 figure 6 architecture of repeater application 1.5.4 wireless local loop in figure 7 an example for base station configuration is sketched. the peb/f 2091 version 5.3 is designed to suit to peb 24911/peb 24902 (dfe-q/afe) in the linecard, and to the pmb 2727 (multichannel burst mode controller) in the base station. several special features concerning s/g bit control (see "s/g bit and bac bit operations", page 198) allow flexible and cost effective construction of base station boards without the need for external circuitry for s/g bit evaluation. like the s/g bit, the s/g pin can be used for transmitting a common synchronization pulse to the burst mode controller. moreover the undervoltage detection feature (see "undervoltage detection", page 92) can be used to monitor power supply drops on the board. peb/f 2091 nt-rp peb/f 2091 lt-rp p interface p u interface u interface pll xin upstream upstream fsc dd du 15.36 mhz 15.36 mhz rst dcl cls peb 2091 pef 2091 overview semiconductor group 26 data sheet 01.99 figure 7 architecture of the wireless local loop base station 1.5.5 te applications one example for terminal application is the isdn feature phone. figure 8 te application u interface peb/f 2091 peb/f 2091 burst mode controller peb/f 2091 iom ? -2 sg sg microcontroller u interface u interface sg p i/f p i/f air interface iom ? -2 rst iom ? -2 iec-q peb/f 2091 u interface icc peb 2070 microcontroller arcofi ? psb 2163 iom ? -2 peb 2091 pef 2091 overview semiconductor group 27 data sheet 01.99 1.5.6 dual mode u and s terminals and pc cards in this application the iom ? -2 interface can be programmed to be inactive in the iom ? -2 master mode. this allows introduction of dual mode terminals and pc adapter cards using e.g. ipac. see 3.2.4, page 53 for details. figure 9 dual mode pc adapter card peb/f 2091 v5.3 ipac psb 2115 interface logic s interface u interface pots host interface optional ice p i/f p i/f iom ? -2 peb 2091 pef 2091 overview semiconductor group 28 data sheet 01.99 1.5.7 nt-pbx figure 10 nt-pbx application u interface iec-q peb/f 2091 epic ? peb 2056 microprocessor p i/f (optional) p i/f pcm pbx iec-q peb/f 2091 u interface idec ? peb 2075 idec ? peb 2075 1 8 iom ? -2 upstream peb 2091 pef 2091 overview semiconductor group 29 data sheet 01.99 1.5.8 lt application and access network note 1: for lt applications in general it is recommended to use the device kit peb 24911 / peb/f 24902 (quad iec dfe-q/afe), which offers the same function for four metallic lines. in some special configurations, however, (e.g. line cards with 6 lines) it might be more cost effective to use the iec-q. in the configuration below system integration on existing boards is sketched. an lt configuration with up to 8 iec-qs can be built with an epic ? and two idec ? s. the epic ? controls the c/i-channel, the b-channel slot assignment and the monitor channel handling. the idec ? is a hdlc-controller for four independent d-channels. figure 11 lt and access network applications u interface iec-q peb/f 2091 v5.3 epic ? peb 2056 microprocessor p i/f (optional) p i/f pcm peb/f 2091 v5.3 u interface idec ? peb 2075 idec ? peb 2075 1 8 iom ? -2 upstream peb 2091 pef 2091 overview semiconductor group 30 data sheet 01.99 1.5.9 nt1 note 2: in new designs the iec-q is not recommended for this application. it is more cost effective and more convenient to use peb/f 8091 in this application. as the peb/f 8091 combines the functionality of sbc-x and iec-q in one device the combination below is sketched for reference only. figure 12 nt1 application iec-q peb/f 2091 u interface sbcx peb/f 2081 s interface iom ? -2 ntc-q peb/f 8091 peb 2091 pef 2091 pin descriptions semiconductor group 31 data sheet 01.99 2 pin descriptions the peb/f 2091 is available in three packages, p-lcc-44, t-qfp-64 and m-qfp-64. the detailed pin configurations of these three packages are given in section 2.1 below. section 2.2 on page 32 provides a detailed definition and a brief functional description of all pins, for both stand-alone and microprocessor modes. section 2.3 on page 48 closes this chapter with an overview of different p interface modes supported by the iec-q. 2.1 pin configuration 2.1.1 p-lcc-44 package figure 13 pin configuration for p-lcc-44 package (top view) 40 29 3&:5 $'' 3&5' $'' 3&'$'' 3&'$'' 3&'$'' *1'$ $287 763&6 %287 9 ' ' ' 9 ' ' ' 9 ''$ 9 5() ;287 ;,1 9 ''$ 302'( 9 ''$ %,1 $,1 *1'$ '2':5 5: 3&$$'' 3&$$'' ',660&/. 76$&',1 76$&'287 0725' '6 73 )6& '&/ &/6 76$ ,17,17 73$/(&&/. 36 36 *1'' $872567 5(6 %8567$602'( /7$'' ',1 '287 peb/f 2091 v5.3 41 42 43 44 1 2 3 4 5 6 28 27 26 25 24 23 22 21 20 19 18 30 31 32 33 34 35 36 37 38 39 17 16 15 14 13 12 11 10 9 8 7 peb 2091 pef 2091 pin descriptions semiconductor group 32 data sheet 01.99 2.1.2 t-qfp-64 and m-qfp-64 packages figure 14 pin configuration for m-qfp-64 and t-qfp-64 packages (top view) 2.2 pin definitions and functions the following tables group the pins according to their functions. they include pin name, pin number, type and a brief description of the function. 12345678910111213141516 17 18 19 20 26 27 28 29 30 22 24 21 25 23 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 55 54 53 52 51 59 57 60 56 58 50 49 3&:5 $'' 3&5' $'' 3&'$'' 3&'$'' 3&'$'' 1& *1'$ 1& $287 763&6 %287 9 ' ' ' 9 ' ' ' 1& 1& 9 ' ' ' 1& 9 ''$ 1& 9 5() ;287 ;,1 1& 9 ''$ 1& 1& 302'( 9 ''$ %,1 $,1 *1'$ '2':5 5: ,&( 1& 3&$$'' 3&$$'' ',660&/. 76$&',1 76$&'287 0725' '6 1& 1& 73 )6& '&/ &/6 76$ 1& 1& 1& ,17,17 73$/(&&/. 36 36 *1'' $872567 5(6 %8567$602'( 1& 6* /7$'' ',1 '287 1& peb/f 2091 v5.3 peb 2091 pef 2091 pin descriptions semiconductor group 33 data sheet 01.99 2.2.1 pin definition in stand-alone mode (i.e. pmode="0" or unconnected) pin no. p-lcc-44 pin no. t-qfp64 m-qfp64 symbol input (i) output (o) function 2.2.1.1 mode selection pins 12 24 pmode i processor interface enable: tie to gnd or do not connect to select stand-alone mode. setting pmode to "1" enables the processor interface, see "pin definition in microprocessor mode", page 40. internal pull down. 28 47 res i reset: low active, must be (0) at least for 30 ns, (see table 4, page 53 for complete description of available mode configurations with this pin). the reset in the lt and nt-pbx mode will be carried out only after the clocks on the iom ? -2 have been applied to the iec-q. tie to vdd if not used. 3 10 tsp i single pulse test mode: for activation refer to table 4, page 53. when active, alternating 2.5 v pulses are issued in 1.5 ms intervals. tie to gnd if not used. 25 44 lt i/o lt modes: selects lt, cot 512/1536, lt-rp (1) and non lt modes nt, te, nt-pbx, nt-rp (0). see table 2, page 51 for details on mode selection. 24 43 burst i selection of burst modes (lt, nt-pbx) with (1) and non-burst modes (nt, te, cot-512/1536, lt/nt-rp) with (0). see table 2, page 51 for details on mode selection. peb 2091 pef 2091 pin descriptions semiconductor group 34 data sheet 01.99 33 55 ts0 i time-slot: iom ? -2 channel selection for burst mode. lsb, active high. see table 2, page 51 for details on mode selection. 35 58 ts1 i/o time-slot: iom ? -2 channel selection for burst mode. active high. see table 2, page 51 for details on mode selection. 36 59 ts2 i time-slot: iom ? -2 channel selection for burst mode. msb, active high. see table 2, page 51 for details on mode selection. 18 35 auto i/o auto: selection between auto and transparent mode for eoc channel processing. (auto mode = (1)) 2.2.1.2 power supply pins 1, 2 7, 8, 12 v ddd i5 v 5% digital supply voltage 5 14 gnda1 i 0 v analog 7, 8 18, 19 v dda1 i5 v 5% analog supply voltage 921 v ref o v ref pin to buffer internally generated voltage. connect a capacitor of 100 nf to gnd 13 26 v dda2 i5 v 5% analog supply voltage 16 30 gnda2 i 0 v analog 23 41 gndd i 0 v digital pin no. p-lcc-44 pin no. t-qfp64 m-qfp64 symbol input (i) output (o) function peb 2091 pef 2091 pin descriptions semiconductor group 35 data sheet 01.99 2.2.1.3 iom ? -2 pins 31 53 dcl i/o data clock: clock range 512 khz to 4096 khz. 30 52 fsc i/o frame synchronization clock: the start of the b1-channel in time-slot 0 is marked. fsc = (1) for one dcl-period indicates a superframe marker. fsc = (1) for at least two dcl-periods marks a standard frame. 26 45 din i data in: input of iom ? -2 data synchronous to dcl-clock. corresponds to dd (data downstream) in lt and du (data upstream) in nt applications. 27 46 dout o data out: output of iom ? -2 data synchronous to dcl-clock. corresponds to dd (data downstream) in nt and du (data upstream) in lt applications. 2.2.1.4 iom ? -2 control pins 17 32 dod i dout open drain: select open drain with dod = (1) (external pull-up resistor required) and tristate with dod = (0). 34 57 mto i monitor procedure time-out: disables the internal 6 ms monitor time-out when set to (1). internal pull-down resistor. pin no. p-lcc-44 pin no. t-qfp64 m-qfp64 symbol input (i) output (o) function peb 2091 pef 2091 pin descriptions semiconductor group 36 data sheet 01.99 2.2.1.5 u-interface pins 15 29 ain i differential u-interface input: connect to hybrid. 14 28 bin i differential u-interface input: connect to hybrid. 6 16 aout o differential u-interface output: connect to hybrid. 4 13 bout o differential u-interface output: connect to hybrid. 2.2.1.6 power controller pins 44 5 pcd0 i/o data bus of power controller interface: lsb. connect to vdd if not used. 43 4 pcd1 i/o data bus of power controller interface: connect to vdd if not used. 42 3 pcd2 i/o data bus of power controller interface: msb. connect to vdd if not used. 39 62 pca0 i/o address bus of power controller interface. 38 61 pca1 i/o address bus of power controller interface. 41 2 pcrd i/o power controller interface read request: low active. 40 1 pcwr i/o power controller interface write request: low active. 19 36 int i/o interrupt: change-sensitive. after a change of level has been detected the c/i code "int" will be issued on iom ? -2. tie to gnd if not used. pin no. p-lcc-44 pin no. t-qfp64 m-qfp64 symbol input (i) output (o) function peb 2091 pef 2091 pin descriptions semiconductor group 37 data sheet 01.99 37 60 diss o disable power supply: different function in lt and nt modes. lt: the diss pin is set to (1) with the c/i command "ltd". nt: the diss pin is set to (1) after receipt of mon-0 lbbd in auto mode. 21 38 ps1 i power status (primary): different function in lt and nt mode. lt: (1) indicates that the remote power is switched off. (1) on ps1 results in c/i message "hi". clamp to low if not used. nt: (1) indicates that prim. power supply is ok. the pin value is identical to the overhead bit "ps1" value. 22 39 ps2 i power status (secondary): different function in lt and nt mode. lt: the current feed value is transmitted (8 bit serially) from a power controller. read the value with mon-8 "rpfc". nt: (1) indicates that secondary power supply is ok. the pin value is identical to the overhead bit "ps2" value. 2.2.1.7 clocks 10 22 xout o crystal out: 15.36-mhz crystal is connected. suitable load capacitances should be connected in parallel. their value depends on the crystal chosen and board layout. see "oscillator circuit and crystal", page 252 for details. leave open if not used. pin no. p-lcc-44 pin no. t-qfp64 m-qfp64 symbol input (i) output (o) function peb 2091 pef 2091 pin descriptions semiconductor group 38 data sheet 01.99 11 23 xin i crystal in: external 15.36-mhz clock signal or 15.36-mhz crystal is connected. in case a crystal is connected, suitable load capacitances should be connected in parallel. their value depends on the crystal chosen and board layout. see "oscillator circuit and crystal", page 252 for details 32 54 cls o clock signal: in the nt modes this clock is synchronized to u-interface. used to synchronize external pll or to clock s-interface devices. in the nt , nt-auto activation, cot- and te modes a 7.68 mhz clock is provided on this pin. in the pbx- and in the lt-rp modes a 512 khz clock is provided. in the nt-rp mode a 15.36 mhz clock is provided (not synchronized to u-interface). in the lt mode the clock on cls is not defined and should therefore be left unconnected. pin no. p-lcc-44 pin no. t-qfp64 m-qfp64 symbol input (i) output (o) function peb 2091 pef 2091 pin descriptions semiconductor group 39 data sheet 01.99 2.2.1.8 miscellaneous function pins not available 64 ice i iom ? -2 clocks enable in iom ? -2 master modes: 0: no fsc and dcl clocks are output. clocks may be applied to pins fsc and dcl. however, they are ignored by the iec-q. data on pin din is ignored. pin dout is floating. 1: behavior as in former versions of the iec-q. the iom ? -2 clocks fsc and dcl are output on the corresponding pins. due to an internal 100kohm pull-up resistor this is the default configuration after reset if pin ice is not connected. this pin can be overridden by the bit adf2:icec. for more information see "iom ?-2 enable/disable mode", page 53. in iom ? -2 slave modes: connect to vdd or leave open. internal pull up. not available 42 sg o undefined in stand-alone mode. leave it open 2.2.1.9 test pins 29 51 tp i test pin: not available to user. do not connect. internal pull-down resistor. 20 37 tp1 i test pin: not available to user. do not connect. internal pull-down resistor. pin no. p-lcc-44 pin no. t-qfp64 m-qfp64 symbol input (i) output (o) function peb 2091 pef 2091 pin descriptions semiconductor group 40 data sheet 01.99 2.2.2 pin definition in microprocessor mode (i.e. pmode="1") pin no. p-lcc-44 pin no. t-qfp64 m-qfp64 symbol input (i) output (o) function 2.2.2.1 mode selection pins 12 24 pmode i processor interface enable: pmode must be set to "1" to enable the processor interface (multiplexed, demultiplexed and serial modes). tie to gnd or do not connect to select stand-alone mode, see "pin definition in stand-alone mode", page 33. internal pull down. 28 47 res i reset: low active, must be (0) at least for 30 ns, (see table 4, page 53 for complete description of available mode configurations with this pin. the reset in the lt and nt-pbx mode will be carried out only after the iom ? -2 clocks have been applied to the iec-q. tie to vdd if not used. 2.2.2.2 data, address and p selection pins 24 43 smode i serial mode pin: smode = 1 selects serial mode, smode = 0 enables the multiplexed mode. a0 address bus pin (demultiplexed mode). smode (multiplexed mode) tie to gnd 36 59 cdin i controller data in (serial mode): cclk determines the data rate. a1 address bus pin (demultiplexed mode). not used (multiplexed mode) tie to gnd. peb 2091 pef 2091 pin descriptions semiconductor group 41 data sheet 01.99 35 58 cdout i/o controller data out (serial mode): cclk determines the data rate. cdout is "high z" if no data is transmitted. a2 i/o address bus pin (demultiplexed mode). not used (multiplexed mode) tie to gnd. 33 55 not used i (serial mode) tie to gnd. a3 address bus pin (demultiplexed mode). not used (multiplexed mode) tie to gnd. 44 5 not used i/o (serial mode) tie to gnd. d0 data bus pin (demultiplexed mode) ad0 address/data bus pin (multiplexed mode) 43 4 not used i/o (serial mode) tie to gnd. d1 data bus pin (demultiplexed mode) ad1 address/data bus pin (multiplexed mode) 42 3 not used i/o (serial mode) tie to gnd. d2 data bus pin (demultiplexed mode) ad2 address/data bus pin (multiplexed mode) 41 2 not used i/o (serial mode) tie to gnd. d3 data bus pin (demultiplexed mode) ad3 address/data bus pin (multiplexed mode) 40 1 not used i/o (serial mode) tie to gnd. d4 data bus pin (demultiplexed modes) ad4 address/data bus pin (multiplexed mode) pin no. p-lcc-44 pin no. t-qfp64 m-qfp64 symbol input (i) output (o) function peb 2091 pef 2091 pin descriptions semiconductor group 42 data sheet 01.99 39 62 not used i/o (serial mode) tie to gnd. d5 data bus pin (demultiplexed modes) ad5 address/data bus pin (multiplexed mode) 38 61 not used i/o (serial mode) tie to gnd. d6 data bus pin (demultiplexed modes) ad6 address/data bus pin (multiplexed mode) 25 44 not used i/o (serial mode) tie to gnd. d7 data bus pin (demultiplexed modes) ad7 address/data bus pin (multiplexed mode) 2.2.2.3 p control pins 19 36 int i/o interrupt line (multiplexed, demultiplexed and serial modes): low active. 310cs i chip select (multiplexed, demultiplexed and serial modes): low active. 17 32 not used i (serial mode) tie to gnd. wr write (siemens/intel multiplexed and demultiplexed modes): indicates a write operation, active low. r/w read/write (motorola demultiplexed mode): indicates a read (high) or write (low) operation. pin no. p-lcc-44 pin no. t-qfp64 m-qfp64 symbol input (i) output (o) function peb 2091 pef 2091 pin descriptions semiconductor group 43 data sheet 01.99 34 57 not used i (serial mode) tie to gnd. rd read (siemens/intel multiplexed and demultiplexed modes): indicates a read operation, active low. ds data strobe (motorola demultiplexed mode): indicates a data transfer, active low. 20 37 cclk i controller data clock (serial mode): shifts data from or to the device. (mode select) mode selection (demultiplexed mode): ale tied to gnd selects the siemens/intel type. ale tied to vdd selects the motorola type. ale i address latch enable (multiplexed mode): in the siemens/intel p interface modes a high indicates an address on the ad0..3 pins which is latched with the falling edge of ale. 2.2.2.4 power supply pins 1, 2 7, 8, 12 v ddd i5 v 5% digital supply voltage 5 14 gnda1 i 0 v analog 7, 8 18, 19 v dda1 i5 v 5% analog supply voltage 921 v ref o v ref pin to buffer internally generated voltage. connect a capacitor of 100 nf to gnd 13 26 v dda2 i5 v 5% analog supply voltage 16 30 gnda2 i 0 v analog 23 41 gndd i 0 v digital pin no. p-lcc-44 pin no. t-qfp64 m-qfp64 symbol input (i) output (o) function peb 2091 pef 2091 pin descriptions semiconductor group 44 data sheet 01.99 2.2.2.5 iom ? -2 pins 31 53 dcl i/o data clock: clock range 512 khz to 4096 khz. 30 52 fsc i/o frame synchronization clock: the start of the b1-channel in time-slot 0 is marked. fsc = (1) for one dcl-period indicates a superframe marker. fsc = (1) for at least two dcl-periods marks a standard frame. 26 45 din i data in: input of iom ? -2 data synchronous to dcl-clock. corresponds to dd (data downstream) in lt and du (data upstream) in nt applications. 27 46 dout o data out: output of iom ? -2 data synchronous to dcl-clock. corresponds to dd (data downstream) in nt and du (data upstream) in lt applications. 2.2.2.6 u-interface pins 15 29 ain i differential u-interface input: connect to hybrid. 14 28 bin i differential u-interface input: connect to hybrid. 6 16 aout o differential u-interface output: connect to hybrid. 4 13 bout o differential u-interface output: connect to hybrid. pin no. p-lcc-44 pin no. t-qfp64 m-qfp64 symbol input (i) output (o) function peb 2091 pef 2091 pin descriptions semiconductor group 45 data sheet 01.99 2.2.2.7 power controller pins 21 38 ps1 i power status (primary): different function in lt and nt mode. lt: (1) indicates that the remote power is switched off. (1) on ps1 results in c/i message "hi". clamp to low if not used. nt: (1) indicates that primary power supply is ok. the pin value is identical to the overhead bit "ps1" value. 22 39 ps2 i power status (secondary): different function in lt and nt mode. lt: the current feed value is transmitted (8 bit serially) from a power controller. read the value with mon-8 "rpfc". nt: (1) indicates that secondary power supply is ok. the pin value is identical to the overhead bit "ps2" value. 2.2.2.8 clocks 10 22 xout o crystal out: 15.36-mhz crystal is connected. suitable load capacitances should be connected in parallel. their value depends on the crystal chosen and board layout. see "oscillator circuit and crystal", page 252 for details. leave open if not used. pin no. p-lcc-44 pin no. t-qfp64 m-qfp64 symbol input (i) output (o) function peb 2091 pef 2091 pin descriptions semiconductor group 46 data sheet 01.99 11 23 xin i crystal in: external 15.36-mhz clock signal or 15.36-mhz crystal is connected. in case a crystal is connected, suitable load capacitances should be connected in parallel. their value depends on the crystal chosen and board layout. see "oscillator circuit and crystal", page 252 for details 32 54 cls o clock signal: in the nt modes this clock is synchronized to u-interface. used to synchronize external pll or to clock s-interface devices. in the nt, nt-auto activation, cot and te modes a 7.68 mhz clock is provided on this pin. in the pbx- and in the lt-rp modes a 512 khz clock is provided. in the nt-rp mode a 15.36 mhz clock is provided (not synchronized to u-interface). in the lt mode the clock on cls is not defined and should therefore be left unconnected. 37 60 mclk o microprocessor clock output (multiplexed, demultiplexed and serial modes): provided with four programmable clock rates: 7.68 mhz, 3.84 mhz, 1.92 mhz and 0.96 mhz. 2.2.2.9 miscellaneous function pins 18 35 rst o reset output (multiplexed, demultiplexed and serial modes): low active. pin no. p-lcc-44 pin no. t-qfp64 m-qfp64 symbol input (i) output (o) function peb 2091 pef 2091 pin descriptions semiconductor group 47 data sheet 01.99 not available 64 ice i iom ? -2 clocks enable in iom ? -2 master modes: 0: no fsc and dcl clocks are output. clocks may be applied to pins fsc and dcl. however, they are ignored by the iec-q. data on pin din is ignored. pin dout is floating. 1: behavior as in former versions of the iec-q. the iom ? -2 clocks fsc and dcl are output on the corresponding pins. due to an internal 100 kohm pull-up resistor this is the default configuration after reset if pin ice is not connected. this pin can be overridden by the bit adf2:icec. for more information see "iom ?-2 enable/disable mode", page 53. in iom ? -2 slave modes: connect to vdd or leave open. internal pull up. not available 42 sg o stop/go bit status pin gives the status of the s/g bit in te mode if the s/g bit control function is being used, see "indication of s/g bit status on pin sg", page 205, for details. in all other modes the sg pin in set to 1. 2.2.2.10 test pin 29 51 tp i test pin: not available to user. do not connect. internal pull-down resistor. pin no. p-lcc-44 pin no. t-qfp64 m-qfp64 symbol input (i) output (o) function peb 2091 pef 2091 pin descriptions semiconductor group 48 data sheet 01.99 2.3 microprocessor bus interface (overview) the table below gives an overview of the different microprocessor bus modes. table 1 microprocessor bus interface pin number stand-alone mode symbol in processor mode p-lcc-44 t-qfp-64 and m-qfp-64 siemens/ intel multiplexed siemens/ intel demultiplex. motorola demultiplex. serial 12 24 pmode = 0 pmode = 1 44 5 pcd0 ad0 d0 d0 n.c. 43 4 pcd1 ad1 d1 d1 n.c. 42 3 pcd2 ad2 d2 d2 n.c. 41 2 pcrd ad3 d3 d3 n.c. 40 1 pcwr ad4 d4 d4 n.c. 39 62 pca0 ad5 d5 d5 n.c. 38 61 pca1 ad6 d6 d6 n.c. 25 44 lt ad7 d7 d7 n.c. 19 36 int int int int int 24 43 burst smode=0 a0 a0 smode=1 36 59 ms2 n.c. a1 a1 cdin 35 58 ms1 n.c. a2 a2 cdout 33 55 ms0 n.c. a3 a3 n.c. 20 37 tp1 ale ale=0 ale=1 cclk 34 57 mto rd rd ds n.c. 17 32 dod wr wr r/w n.c. 310tsp cs cs cs cs 37 60 diss mclk 18 35 auto rst peb 2091 pef 2091 functional description semiconductor group 49 data sheet 01.99 3 functional description interfaces and functional blocks of the peb/f 2091 v5.3 differ depending on the mode used, i.e. depending on whether the stand-alone mode or the microprocessor mode is being used. section 3.1 defines these two modes and gives an overview of device function. as mentioned in section 1.1, page 19 the iec-q can be used in various functional modes, including lt, nt, te, repeater and others. section 3.2 gives an overview of available modes, and describes how these modes can be set. in addition an overview is given about setting special modes, e.g. test modes, and eoc auto and transparent modes and different mode settings related to the iom ? -2 interface. in section 3.3 device architecture is discussed. block diagrams for both stand-alone and microprocessor modes are illustrated. section 3.4 describes the architecture of the u-interface core (transceiver core). it provides a brief description of its functions and properties. the devices interfaces defined in section 3.3 are described in the subsequent sections 3.5 through 3.14. all relevant functional information about these interfaces, especially those related to users handling are given. the interaction between these interfaces, however, is out of the scope of this section (e.g. operations between the iom ? -2 and the u-interface). this is the scope of the chapter "operational description", page 96. section 3.15 gives an overview of the reset behavior of the iec-q. 3.1 functional overview the iec-q fulfills all u transceiver functions required by all national and international standardization institutes. it also provides simple and flexible access to data and control bits on the u-interface, activation and deactivation, monitoring transmission quality and other useful general as well as application specific functions. this access can be achieved using the iom ? -2 interface, the microprocessor interface or a combination of both. if the microprocessor interface is not being used we refer to this mode as stand-alone mode. this mode can be selected by leaving pin pmode opened or setting it to 0 (see "mode selection pins", page 33). in stand-alone mode the peb/f 2091 v5.3 is controlled exclusively via the iom ? -2 interface and mode selection pins (see figure 15 below). in this mode a power controller interface is available, allowing direct access to e.g. peripheral power controller devices. if the microprocessor interface (pi) is being used we refer to this mode as the p mode. this mode can be selected by setting pin pmode to 1 (see "mode selection pins", page 40). the pi of the peb/f 2091 v5.3 establishes the access of a microprocessor between u-interface and iom ? -2. its main function is illustrated in figure 15. peb 2091 pef 2091 functional description semiconductor group 50 data sheet 01.99 figure 15 stand-alone mode (left) and p mode (right) in p mode b channels, d channel, c/i codes and monitor commands can either be passed between the u transceiver and iom ? -2 directly, or they can be looped through the p via the pi. any selection of "passed" or "looped" channels can be programmed via a control register. 3.2 setting operating modes mode setting of the peb/f 2091 v5.3 will be described in several subsections below. this includes setting basic operation modes (e.g. lt, nt, repeater), as well as setting special operating modes, i.e. test modes, dout driver modes, iom ? -2 enable/disable, eoc auto/transparent and monitor time-out on/off. setting operation modes of the peb/f 2091 v5.3 will be different in stand-alone and in p mode. these two cases will be distinguished. 3.2.1 basic operating mode p mode in p mode a microprocessor interface gives access to the configuration registers. the basic operating mode is selected via bits stcr:burst,lt, ts2,ts1,ts0, according to table 2, page 51 . the stcr register is described on page 212. stand-alone mode in stand-alone mode the operating mode is selected via pin strapping of pins lt, burst, ts2, ts1 and ts0 according to table 2, page 51. it is possible to change the mode of a device during operation (e.g. for test purposes) if the mode change is followed by a reset. its10193 fsc pi u u r iom -2 r iom -2 peb 2091 pef 2091 functional description semiconductor group 51 data sheet 01.99 table 2 setting modes of operation (stand-alone and p mode) mode selection stand-alone mode/p mode output pins u synchronized mode burst 1) 1) in stand-alone mode this name refers to the corresponding pin in p mode this name refers to the corresponding bit in register stcr lt 1) ts2 1) ts1 1) ts0 1) dcl in dcl out (khz) cls out (khz) super frame marker 2) 2) 1 dcl-period high-phase of fsc at superframe position 2 dcl-periods high-phase of fsc at normal position nt 0 0000_5127680 3) 3) cls-clock signal not available while device is in power-down. synchronized to the u-interface no nt 0 0100_5127680 3) yes nt-auto activation 0 0001_5127680 3) no te 0 0010_15367680 3) no te 0 0110_15367680 3) yes nt-pbx 1 0 iom ? -2 channel assignment (table 3) 512- 4096 _512 3) _ lt 1 1 iom ? -2 channel assignment (table 3) 512- 4096 _not defined _ cot-5120 1000_5127680 4) 4) cls-clock signal available while device is in power-down. not synchronized to the u-interface no cot-15360 1010_15367680 4) no lt-rp0 1101512_ 512 4) _ nt-rp0 0101_51215360 4) yes peb 2091 pef 2091 functional description semiconductor group 52 data sheet 01.99 3.2.2 test modes p mode test modes send single pulses, quiet mode or data through are invoked via the corresponding c/i channel command (see "c/i channel codes", page 224) or via bits stcr:tm2,tm1 (table 4). see also "stcr-register", page 212. stand-alone mode the test modes send single pulses (ssp), quiet mode (qm) and data through (dt) are invoked via the corresponding c/i channel command ("c/i channel codes", page 224) or via pins res and tsp (table 4). table 3 setting iom ? -2 channel assignment iom ? -2 channel no. ts2 1) 1) in stand-alone mode this name refers to the corresponding pin. the pin value is read continuously (non-latching) after the supply voltage has reached its nominal value in p mode this name refers to the corresponding bit in register stcr ts1 1) ts0 1) bit no. min. frequency of dcl (khz) ch 0 0 0 0 0 31 512 ch 1 00132 63 1024 ch 2 01064 95 1536 ch 3 01196 127 2048 ch 4 100128 159 2560 ch 5 101160 191 3072 ch 6 110192 223 3584 ch 7 111224 255 4096 peb 2091 pef 2091 functional description semiconductor group 53 data sheet 01.99 3.2.3 dout driver modes mode setting of pin dout will be given in the following two tables 3.2.4 iom ? -2 enable/disable mode note 3: this mode setting is only available in the master mode of the iec-q, i.e. modes in which the iom ? -2 clocks fsc and dcl are delivered by the table 4 setting test modes mode selection stand-alone mode/p mode test-mode pin res/ bit tm1 pin tsp/ bit tm2 master-reset 1) 1) used for quiet mode and return loss measurements 00 send single-pulses 2) 2) used for pulse mask measurements 11 data-through 3) 3) used for insertion loss, power spectral density and total power measurements 01 normal operation 1 0 table 5 setting dout driver in stand-alone mode mode pin res pin tsp pin dod pin dout output driver value dout in active iom ? -2 channel 1) 1) refer to notes 10, page 72, 12, page 72, and 15, page 73 for explanation about active and passive channels dout in passive iom ? -2 channel 1) normal (tristate) 1 0 0 0 low high z 1high normal (open drain 2) ) 2) external pull-up resistors required (typ.1 k w ) 1 0 1 0 low floating 1 floating peb 2091 pef 2091 functional description semiconductor group 54 data sheet 01.99 iec-q. see table 2, page 51. for a detailed description of the iom ? -2 interface refer to section 3.6, page 70. applications in which the iec-q is not the only potential iom ? -2 clock master on the board have to deal with iom ? -2 clock conflicts during and after reset. among these applications are dual mode s- or u-terminals and circuits (see "dual mode u and s terminals and pc cards", page 27). typical applications would include the isac ? -s te (psb 2186) or the ipac (psb 2115) in te mode. both devices output fsc and dcl during and after reset. the peb/f 2091 v5.3 in the 64 pin packages (t-qfp-64 or m-qfp-64) has a pin (pin 64, ice) which allows to enable or disable the iom ? -2 clocks and the data-lines. it is possible to change the status of pin ice without the need of a reset signal being applied. in p mode the status of pin ice can be overridden by bit adf2:icec. basically, the value of pin ice and the bit-value are exored (see table 7 below). this function can also be controlled in the p-lcc-44 package in the microprocessor mode (pmode = "1") by bit adf2:icec, see "adf2-register", page 214. the following table gives an overview of the control mechanisms of this function in different settings. the terms "idle" and "active" of the iom ? -2 interface in table 7 are defined as follows: idle means that no fsc and dcl clocks are output. clocks may be applied to pins fsc and dcl. however, they are ignored by the iec-q. data on pin din is ignored. internally, the din signal will be clamped to 1. pin dout is floating, which is the same behavior as described in "dout driver modes", page 53. table 6 setting dout driver in p mode mode pin res bit adf2: dod 1) pin dout output driver value dout in active iom ? -2 channel 2) dout in passive iom ? -2 channel normal (tristate) 1 0 0 low high z 3) 1high normal (open drain 4) ) 1 1 0 low floating 1 floating 1) see also "adf2-register", page 214 2) refer to notes 10, page 72, 12, page 72, and 15, page 73 for explanation about active and passive channels 3) in te mode bit number 27 of channel 2 (s/g bit) may be driven if the s/g bit control function is being used (see "s/g bit and bac bit operations", page 198) 4) external pull-up resistors required (typ.1 k w ) peb 2091 pef 2091 functional description semiconductor group 55 data sheet 01.99 active means that the behavior is as in former versions of the iec-q. the iom ? -2 clocks fsc and dcl are output on the corresponding pins. due to the 100 kohm pull-up resistor this is the default configuration after reset if pin ice is not connected. 3.2.5 eoc auto/transparent mode the u-interface eoc (embedded operations channel) allows transmission of commands and informations in either direction of the u-interface. for details on eoc structure and commands, see "predefined eoc codes", page 231. if the eoc "transparent" mode is selected eoc channel informations will be given transparently on the iom ? -2 interface independently of the content of the eoc channel. in the eoc "auto" mode an eoc processor is activated for eoc command interpretation and handling. for operational details of the eoc in both modes see "access to eoc of u-interface", page 110. in stand-alone mode the eoc mode will be set by the input pin auto. in p mode the eoc mode will be set by bit auto of register stcr (see "stcr-register", page 212). 3.2.6 monitor procedure time-out (mto) the iec-q offers an internal reset (monitor procedure "time-out") for the monitor procedure (see 3.6.3, page 76 for description of the iom ? -2 monitor channel). this reset table 7 setting iom ? -2 clock enable/disable mode mode package adf2:icec bit polarity ice pin polarity iom ? -2 interface stand-alone mode (pmode= "0" or unconnected) p-lcc-44 not available not available active m-qfp-64 or t-qfp-64 not available "1" or not connected active "0" idle p mode (pmode="1") p-lcc-44 "0" (default) not available active "1" idle m-qfp-64 or t-qfp-64 "0" (default) "1" or not connected active "0" idle "1" "1" or not connected idle "0" active peb 2091 pef 2091 functional description semiconductor group 56 data sheet 01.99 function transfers the monitor channel into the idle state thereby resolving possible lock-up situations. it therefore is to be used in all systems where no m p is capable of detecting and solving hang-up situations in the monitor procedure. for a detailed description of the time-out procedure see "monitor procedure time-out", page 80. note 4: the monitor channel time-out feature is only available after the complete receive frame structure has been detected on u (see figure 30, page 81). i.e. this feature is available if the following signals have been received: in lt modes, the signals sn3 or sn3t in nt modes, the signals sl2, sl3, sl3t see "u-interface signals", page 125 for definition of these signals. i n stand-alone mode the mto mode will be set by the input pin mto. in p mode the mto mode will be set by bit mto of register adf2 (see "adf2-register", page 214). 3.2.7 setting iom ? -2 bit clock mode note 5: this section applies only if the microprocessor mode and the iom ? -2 master mode are used (see note 8, page 70 for definition). the default frequency of the iom ? -2 clock dcl will always be two times the bit frequency (see note 7, page 70). in some non standard applications it might be more convenient to have iom ? -2 bit rate on dcl, instead. the iec-q supports this in the microprocessor mode. in this mode it is possible to change the dcl frequency if the iom ? -2 master table 8 setting eoc mode mode selection stand-alone mode / p mode eoc mode pin auto/bit stcr:auto transparent 0 automatic 1 table 9 setting mto mode mode selection stand-alone mode / p mode mto mode pin mto/bit adf2:mto time-out enabled 0 1) 1) in stand-alone mode the pin mto can be left unconnected. due to an internal pull-down the monitor channel time-out feature will be enabled. time-out disabled 1 peb 2091 pef 2091 functional description semiconductor group 57 data sheet 01.99 mode is being used. setting the adf:bcl bit to 1 will change dcl frequency to the bit data rate, dividing the default dcl frequency by 2. note 6: setting this mode will change the output frequency on pin dcl. internally, the iec-q will continue to work with the default dcl frequency. peb 2091 pef 2091 functional description semiconductor group 58 data sheet 01.99 3.3 block diagram microprocessor mode in the microprocessor mode the following interfaces and functional blocks are used. for an overview of block functions refer to sections 3.4 through 3.15. figure 16 device architecture in p mode 0rgh 6hohfwlrq 7hvw &orfnv ,20 ? ,qwhuidfh 8 ,qwhuidfh 7udqvfhlyhu&ruh 89' :' 3rzhu 6wdwxv $287 %287 $,1 %,1 )6& '&/ '287 ',1 0&/. &/6 ;287 ;,1 567 73 36 36 302'( 5(6 ,&( *) available only in m-qfp-64 and t-qfp-64 packages 6*%lw 6wdwxv 6* ?3,qwhuidfh 602'( :5 &6 ,17 5' $/( $'$' peb 2091 pef 2091 functional description semiconductor group 59 data sheet 01.99 stand-alone mode in stand-alone mode the following interfaces and functional blocks are used. for an overview of block functions refer to sections 3.4 through 3.15. figure 17 device architecture in stand-alone mode 0rgh6hohfwlrq 7hvw &orfnv ,20 ? ,qwhuidfh 8 ,qwhuidfh 7udqvfhlyhu&ruh $287 %287 $,1 %,1 )6& '&/ '287 ',1 &/6 ;287 ;,1 73 302'( 5(6 73 $872 763 76 76 76 ,&( *) available only in m-qfp-64 and t-qfp-64 packages 3rzhu&rqwuroohu,qwhuidfh ,17 3&5' 3&:5 3&$ 3&$ 3&' 3&' 3&' 3rzhu 6wdwxv 36 36 ',66 peb 2091 pef 2091 functional description semiconductor group 60 data sheet 01.99 3.4 transceiver core the u transceiver establishes the direct link between the exchange and the terminal side over two copper wires. transmission over the u-interface is performed at a rate of 80 kbaud. two binary informations are coded into one quaternary symbol (2b1q) resulting in a total of 160 kbit/s to be transmitted. 144 kbit/s are user data (2b + d), 16 kbit/s are used for maintenance and synchronization information. for the structure of the u-interface, see "u-interface", page 67. user access to the transceiver core will be established via one of the iec-q interfaces, e.g. iom ? -2 or p interface (see figure16 and 17 above). the access method to the transceiver core and to other blocks of the iec-q will be the scope of chapter 4, "operational description", page 96 ff. peb 2091 pef 2091 functional description semiconductor group 61 data sheet 01.99 figure 18 u transceiver block diagram u (out) iom ? -2/p other interfaces buffer (tr.) sf crc eoc sb control timing recovery adaptive ec adaptive eq agc a d awake d a buffer (rec.) + siu rec liu scr descr u (in) loop peb 2091 pef 2091 functional description semiconductor group 62 data sheet 01.99 the u transceiver can be subdivided in three main blocks: siu system interface unit rec receiver liu line interface unit 3.4.1 system interface unit the system interface unit (siu) provides the link between the different interfaces of the iec-q, e.g. iom ? -2 to the u- interface. transmit buffer this block is a first in first out (fifo) buffer which stores the user data (2b+d) given to the iec-q via iom ? -2 or p interface. these data are then transmitted to the d/a converter (liu) and to the adaptive echocanceller (rec) with the appropriate u-interface timing. receive buffer this is a first in first out (fifo) buffer which stores the user data (2b+d) received from the u-interface. these data are then transmitted to the user interface (iom ? -2 or p) with the appropriate interface timing. scrambler / descrambler the scrambling and descrambling algorithms are implemented in these blocks (scr and descr in figure 18, page 61). these algorithms ensures that no sequences of permanent binary 0s or 1s are transmitted. the algorithms used for scrambling and descrambling in lt and nt modes are described in figure 19. note that one wrong bit decision in the receiver automatically leads to at least three bit errors. peb 2091 pef 2091 functional description semiconductor group 63 data sheet 01.99 figure 19 scrambler / descrambler algorithms x -1 x -1 x -1 x -1 x -1 ds ? x -23 ds ? x -18 ds di transmitter scrambler in nt, nt-pbx and te mode without loop-back 3 x -1 x -1 x -1 x -1 x -1 ds ? x -23 ds ? x -5 ds di transmitter scrambler for all lt modes and for loop-back 3 in all nt modes x -1 x -1 x -1 x -1 x -1 ds ? x -23 ds ? x -18 ds do receiver descrambler in nt, nt-pbx and te mode without loop-back 3 x -1 x -1 x -1 x -1 x -1 ds ? x -23 ds ?x -5 ds do receiver descrambler for all lt modes and for loop-back 3 in all nt modes do = ds (1 x -18 x -23 ) + + do = ds (1 x -5 x -23 ) + + ds = di ds ? x -5 ds ? x -23 + + ds = di ds ? x -18 ds ? x -23 + + peb 2091 pef 2091 functional description semiconductor group 64 data sheet 01.99 control block complete activation and deactivation procedures are implemented, which are controlled by activation and deactivation indications from u, iom ? -2 or p interfaces. state transition of the procedures depend on the actual status of the receiver (adaptation and synchronization) and timing functions to watch fault conditions. embedded operational channel (eoc) processor two different modes can be selected for maintenance functions: in the auto mode all eoc procedure handling and executing as specified by ansi is performed. in the transparent mode all bits are transferred transparently to the users interfaces without any internal processing. see "embedded operations channel (eoc)", page 69 for definition, and "access to eoc of u-interface", page 110 for informations about programming and monitoring the eoc. single bits (sb) processor the single bits are used mainly to communicate status and maintenance functions between the transceivers. the meaning of a bit position depends upon the direction of transmission (upstream/downstream) and the operation mode (repeater or nt/lt). the sb processor interprets these bits and gives access to some of them according to the mode used. it also provides several filtering methods for sb indications. see "single bits channel", page 69 for definition, and "access to the single bits of u-interface", page 115 for informations about programming and monitoring the sb. special functions (sf) this block provides miscellaneous functions of the siu, like the power controller function in stand-alone mode, access to internal chip data, test loops control, s/g bit control in p mode and others. these will be discussed in detail in chapter 4. cyclic redundancy check (crc) the cyclic redundancy check provides a possibility to verify the correct transmission of data. the check sum of a transmitted u-superframe is calculated from the bits in the d-channel, both b-channels, and the m4 bits according to the crc polynomial g (u) = u 12 + u 11 + u 3 + u 2 + u + 1 (+ modulo 2 addition) peb 2091 pef 2091 functional description semiconductor group 65 data sheet 01.99 the check digits (crc bits crc1, crc2, , crc12) generated are transmitted at position m5 and m6 in the u-superframe (see "u-frame structure", page 68). at the receiving side this value is compared with the value calculated from the received superframe. in case these values are not identical a crc-error will be indicated to both sides of the u-interface. in chapter 4.5, page 176, different methods of monitoring transmission quality are discussed in detail. 3.4.2 receiver the receiver block (rec) performs the filter algorithmic functions using digital signal processing techniques. modules for echo cancellation, pre- and post-equalization, phase adaptation and frame detection are implemented in a modular multi-processor concept. 3.4.3 line interface unit the line interface unit (liu) contains the crystal oscillator and all of the analog functions, such as the a/d-converter and the awake unit in the receive path, the pulse-shaping d/a-converter, and the line driver in the transmit path. furthermore it provides an analog test loop-back function. refer also to "analog characteristics", page 266 for detailed information about the electrical characteristics of the liu. analog-to-digital converter the adc was especially developed for the iec-q. it is a sigma-delta modulator of second order using a clock rate of 15.36-mhz. the peak input signal measured between ain and bin must be below 4 vpp. in case the signal input is too low (long range), the received signal is amplified internally by 6 db. the maximum signal to noise ratio is achieved with 1.3 vpp (long range) and 2.6 vpp (short range) input signal voltage. the impedance measured between ain and bin is at least 50 k w . awake block the awake circuit evaluates the differential signal between ain and bin. the differential threshold level is between 4 mv and 28 mv. the dc-level (common mode level) may be between 0 v and 3 v. level detect is not effected by the range setting. digital-to-analog converter the output pulse is shaped by a special dac. the dac was optimized for excellent matching between positive and negative pulses and high linearity. it uses a fully differential capacitor approach. the staircase-like output signal of the dac drives the peb 2091 pef 2091 functional description semiconductor group 66 data sheet 01.99 output buffers. the shape of a dac-output signal is shown below, the peak amplitude is normalized to one. this signal is fed to an rc-lowpass of first order with a corner frequency of 1 mhz 50%. figure 20 dac-output for a single pulse the duration of each pulse is 24 steps, with t0 t = 0.78 m s per step. on the other hand, the pulse rate is 80-khz or one pulse per 16 steps. thus, the subsequent pulses are overlapping for a duration of 8 steps. line driver the line driver is optimized for C high output swing C high linearity C low quiescent current to minimize power consumption the output jitter produced by the transmitter (with jitter-free input signals) is below 0.02 uipp (unit interval = 12.5 m s, peak-peak) measured with a high-pass filter of 30-hz cutoff frequency. without the filter the cutoff jitter is below 0.1 uipp. analog loop-back function an internal analog loop-back function can be activated (see "analog loop-back (no. 1/no. 3)", page 187). this loop-back is closed near the u-interface. if it is active all signals received on ain / bin will neither be evaluated nor recognized. 123456789 15 18 23 x t0 t0 = 0.78 m s 0.25 0.5 0.75 1.0 peb 2091 pef 2091 functional description semiconductor group 67 data sheet 01.99 3.5 u-interface the iec-q interfaces with the metallic line through this block. both are linked by an external circuitry consisting of a transformer and a hybrid circuitry (refer to figure 93, page 250 for details). 3.5.1 output and input signals the output stage comes out of two identical buffers operating in differential mode. this concept allows an output swing of 6.4 vpp between the output pins aout and bout of the iec-q. the nominal peak values of 3 correspond to a 3.2 v peak chip output and 2.5 v peak on the metallic line. the input signal from the metallic line is detected on the differential inputs ain and bin. the swing of the input signal measured must be below 4 vpp. 3.5.2 u -frame structure transmission on the u-interface is performed at a rate of 80 kbaud. the code used is reducing two binary informations to one quaternary symbol (2b1q). data is grouped together into u-superframes of 12 ms each. the beginning of a new superframe is marked with an inverted synchronization word (isw). each superframe consists of eight basic frames which begin with a standard synchronization word (sw) and contain 222 bits of information. the structure of one u-superframe is illustrated in figure 21, and 22. for a detailed description of one complete superframe see table 10, page 68. figure 21 u-superframe structure figure 22 u-basic frame structure out of the 222 information bits 216 contain 2b + d user data, the remaining 6 bits are used to transmit maintenance bits. thus 48 maintenance bits are available per u-superframe. they are used to transmit two eoc-messages (24 bit), 12 overhead bits and one check sum (12 bit). isw 1. basic frame sw 2. basic frame . . . sw 8. basic frame <---12 ms---> (i) sw (inverted) synch word 18 bit (9 quat) 12 2b + d user data 216 bits (108 quat) m1 C m6 maintenance data 6 bits (3 quat) <---1,5 ms---> peb 2091 pef 2091 functional description semiconductor group 68 data sheet 01.99 C isw inverted synchronization word (quat): C 3 C 3 + 3 + 3 + 3 C 3 + 3 C 3 C 3 C sw synchronization word (quat): + 3 + 3 C 3 C 3 C 3 + 3 C 3 + 3 + 3 C crc cyclic redundancy check C eoc embedded operation channel a = address bit d/m = data / message bit i = information (data / message) C act activation bit act = (1) C> layer 2 ready for communication C dea deactivation bit dea = (0) C> lt informs nt that it will turn off C cso cold start only cso = (1) C> nt activation with cold start only C uoa u-only activation uoa = (0) C> u-only activated C sai s-activity indicator sai = (0) C> s-interface is deactivated C febe far-end block error febe = (0) C> far-end block error occurred C ps1 power status primary source ps1 = (1) C> primary power supply ok C ps2 power status secondary source ps2 = (1) C> secondary power supply ok C ntm nt test mode ntm = (0) C> nt busy in test mode C aib alarm indication bit aib = (0) C> interruption (according to ansi) C nib network indication bit nib = (1) C> no function (reserved for network use) table 10 u-frame structure framing 2b + d overhead bits (m1 C m6) quat positions 1 C 9 10 C 117 118s 118m 119s 119m 120s 120m bit positions 1 C 18 19 C 234 235 236 237 238 239 240 super frame # basic frame # sync word2b + dm1m2m3 m4 m5m6 1 1 isw 2b + d eoca1 eoca2 eoca3 act/ act 11 2sw2b + deoc d/m eoci1 eoci2 dea / ps1 1 febe 3 sw 2b + d eoci3 eoci4 eoci5 1/ ps2 crc1 crc2 4 sw 2b + d eoci6 eoci7 eoci8 1/ ntm crc3 crc4 5 sw 2b + d eoca1 eoca2 eoca3 1/ cso crc5 crc6 6sw2b + deoc d/m eoci1 eoci2 1 crc7 crc8 7 sw 2b + d eoci3 eoci4 eoci5 uoa / sai crc9 crc10 8 sw 2b + d eoci6 eoci7 eoci8 aib / nib crc11 crc12 2,3 lt to nt dir. > / < nt to lt dir. peb 2091 pef 2091 functional description semiconductor group 69 data sheet 01.99 embedded operations channel (eoc) eoc-data are available in the u-frame at the positions m1, m2 and m3 thereby permitting the transmission of two complete eoc-messages (2 12 bits) within one u-superframe. the eoc contains an address field, a data/message indicator (d/m) and an eight-bit information field (see table 10, page 68). with the address field the destination of the transmitted message/data is defined. addresses are defined for the nt, 6 repeater stations and broadcasting. the data/message indicator needs to be set to (1) to indicate that the information field contains a message. if set to (0), numerical data is transferred to the nt. currently no numerical data transfer to or from the nt is required. from the 256 codes possible in the information field 64 are reserved for non-standard applications, 64 are reserved for internal network use and eight are defined by ansi/etsi for diagnostic and loop-back functions. all remaining 120 free codes are available for future standardization. for information about eoc channel commands and programming refer to "access to eoc of u-interface", page 110. cyclic redundancy check channel the check digits (crc bits crc1, crc2, , crc12) are transmitted at position m5 and m6 in the u-superframe. this value is compared with the value calculated from the previously received superframe. for more detailed functional information about the crc feature see "cyclic redundancy check (crc)", page 64. single bits channel the single bits in the u-frame are defined to be bits m41 to m48 (eight bits) in addition to the three bits m51, m52 and m61 and the bit febe. bits m41 through m48 will be referred to as m4 bits. the three bits m51, m52 and m61 will be referred to as "additional overhead bits". the single bits are used mainly to communicate status and maintenance functions between the transceivers. the meaning of a bit position depends upon the direction of transmission (upstream/downstream) and the operation mode (repeater or nt/lt). for details about access to these bits, see "access to the single bits of u-interface", page 115. peb 2091 pef 2091 functional description semiconductor group 70 data sheet 01.99 3.6 iom ? -2 interface the iom ? -2 interface is used to interconnect telecommunication ics. it provides a symmetrical full-duplex communication link, containing user data, control/programming and status channels. the structure used follows the 2b + 1d-channel structure of isdn. the isdn user data rate of 144 kbit/s (b1 + b2 + d) is transmitted in both directions over the interface. the iom ? -2 interface is a generalization and enhancement of the iom ? -1 interface. 3.6.1 iom ? -2 frame structure the iom ? -2 interface comprises two clock lines for synchronization and two data lines. data is carried over data upstream (du) and data downstream (dd) signals. the downstream and upstream direction are always defined with respect to the exchange. downstream refers to information flow from the exchange to the subscriber and upstream vice versa respectively. the iom ? -2 interface specification describes open drain data lines with external pull-up resistors. however, if operation is logically point-to-point, tristate operation is possible as well. for iom ? -2 mode setting refer to "setting operating modes", page 50. the data is clocked by a data clock (dcl) that operates at twice the data rate. note 7: this is the default setting. if the microprocessor mode and the master mode are being used, dcl frequency can be set to the bit data rate, see "setting iom ? -2 bit clock mode", page 56 for details. this section will deal with the default setting. nevertheless, it applies to the bit clock mode as well if dcl frequencies are adjusted. frames are delimited by an 8-khz frame synchronization clock (fsc). incoming data is sampled on every second falling edge of the dcl clock. figure 23 iom ? -2 clocks and data lines note 8: a device with an iom ? -2 interface is said to be in the iom ? -2 master mode or sometimes just master mode if the iom ? -2 clocks fsc and dcl are delivered by this device. it is said to be in the iom ? -2 slave mode or sometimes just slave mode if the iom ? -2 clocks are input to this device. peb 2091 pef 2091 functional description semiconductor group 71 data sheet 01.99 within one fsc-period, 32 bit up to 256 bit are transmitted, corresponding to dcl-frequencies ranging from 512 khz up to 4096 khz. three optimized iom ? -2 timing modes exist for: multiplexed timing mode 1) (lt and nt-pbx) plain timing mode (nt, nt-auto activation, cot-512, nt-rp and lt-rp) terminal timing mode (te and cot1536) all applications utilize the same basic frame and clocking structure, but differ in the number and usage of the individual channels. figure 24 basic channel structure of iom ? -2 each frame consists of ? two 64 kbit/s channels b1 and b2 ? the monitor channel for transferring maintenance information ? two bits for the 16 kbit/s d-channel ? four command/indication (c/i) bits for controlling of layer-1 functions (activation/deactivation and other control function) by i.e., layer-2 controller. ? two bits mr and mx for the handshake procedure in the monitor channel 3.6.1.1 multiplexed timing mode note 9: this section applies to the lt and the nt-pbx modes. in multiplexed timing mode the iec-q supports bit rates from 256 kbit/s up to 2048 kbit/s corresponding to dcl-frequencies from 512 khz up to 4096 khz. the typical iom ? -2 line card or nt-pbx application comprises a dcl-frequency of 4096 khz with a nominal bit rate of 2048 kbit/s. therefore eight channels are available, each consisting of the basic frame with a nominal data rate of 256 kbit/s. in lt mode the downstream data (dd) are transferred on pin din, the upstream data (du) on pin dout. in nt-pbx mode the downstream data (dd) are transferred on pin dout, the upstream 1) this mode is also referred to as "burst mode" peb 2091 pef 2091 functional description semiconductor group 72 data sheet 01.99 data (du) on pin din. the iec-q is assigned to an individual channel by pin strapping (see "setting operating modes", page 50). note 10: this assigned channel is called the active channel of the iec-q. all other channels, if available, are called the passive channels of the iec-q. the iom ? -2 signals are: din, dout 256 to 2048 kbit/s dcl 512 to 4096 khz, input fsc 8 khz, input i figure 25 multiplexed frame structure of the iom ? -2 interface 3.6.1.2 plain timing mode note 11: this timing applies to the nt, nt-auto activation, cot-512, lt-rp and nt-rp modes. note 12: note also that the multiplexed mode timing described in 3.6.1.1 will reduce to this timing if the bit rate 256 kbit/s is chosen. in this mode there is therefore only one active iom ? -2 channel. no passive iom ? -2 channels are available. in this timing mode the iec-q provides a data clock dcl with a frequency of 512 khz. as a consequence the iom ? -2 interface provides only one channel with a nominal data rate of 256 kbit/s. itd04319 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 b1 b2 monitor d c/i mm rx fsc dcl du dd ch0 ch0 s 125 r iom r iom peb 2091 pef 2091 functional description semiconductor group 73 data sheet 01.99 the iom ? -2 signals are: din, dout 256 kbit/s dcl 512 khz fsc 8 khz figure 26 plain frame structure of the iom ? -2 interface 3.6.1.3 terminal timing mode note 13: this timing applies to the te and the cot-1536 modes. in the terminal timing mode the iec-q provides a data clock dcl with a frequency of 1536 khz. as a consequence the iom ? -2 interface provides three channels each with a nominal data rate of 256 kbit/s. ? channel 0 contains 144 kbit/s (for 2b+d) plus monitor and command/indication channels for the layer-1 device. ? channel 1 contains two 64-kbit/s intercommunication channels plus monitor and command/indication channels for other iom ? -2 devices. ? channel 2 is used for iom ? -2 bus arbitration (access to the tic bus). only the command/indication bits are used in channel 2. note 14: channels 1 and 2 can be used only in the te mode. the description above for these two channels doesnt apply to the cot-1536 mode. note 15: channel 0 is called the active channel of the iec-q. channels 1 and 2 are called the passive channels of the iec-q. the iom ? -2 signals are: din, dout 768 kbit/s dcl 1536 khz output fsc 8 khz output itd09788 b1 b2 monitor d m rx m c/i b1 b2 monitor d c/i r m x m iom channel 0 r s 125 fsc dd du peb 2091 pef 2091 functional description semiconductor group 74 data sheet 01.99 figure 27 terminal frame structure of the iom ? -2 interface C c/i0 in iom ? -2 channel 0: d: two bits for the 16 kbit/s d-channel c/i: the four command/indication (c/i) bits are used for control of the u transceiver (activation/deactivation and additional control functions). mr , mx: two bits mr and mx for the handshake in the monitor channel 0 C c/i1 in iom ? -2 channel 1: c/i1 to c/i6 are used for control of a transceiver or an other device in iom ? -2 channel 1 (activation/deactivation and additional control functions). mr , mx: two bits mr and mx for handshake in the monitor channel 1 C c/i2 in iom ? -2 channel 2: e: d-echo bits bac-bit (bus accessed). when the tic bus is occupied the bac-bit is low. du / dd d d c/i4 c/i3 c/i2 c/i1 mr mx du / dd c/i6 c/i5 c/i4 c/i3 c/i2 c/i1 mr mx itd09787 dd b1 b2 mon0 c/i0 ic1 ic2 mon1 c/i1 fsc c/i1 mon1 ic2 ic1 c/i0 mon0 b2 b1 du channel 0 c/i2 c/i2 125 m s b1 b1 r iom channel iom r 1 channel r iom 2 peb 2091 pef 2091 functional description semiconductor group 75 data sheet 01.99 s/g-bit (stop/go), available to a connected hdlc controller to determine if it can access the d-channel (s/g = 1: stop, s/g = 0: go). a/b-bit (available/blocked), supplementary bit for d-channel control. (a/b = 1: d-channel available, a/b = 0: d-channel blocked). tba0-2: tic bus address 3.6.2 iom ? -2 command / indication channels the command/indication channels carry real-time control and status information over the iom ? -2 interface. 3.6.2.1 active c/i channel the active c/i channel of the iec-q is available in all operational modes. the channel consists of four bits in each direction. activation and deactivation of the iec-q is always controlled via the active c/i channel. the c/i codes going to the iec-q are called commands, those originating from it are referred to as indications. the iec-q verifies c/i commands with a double last-look criterion, i.e. a new command will be recognized as valid only after it has been correctly detected by the iec-q for two consecutive iom ? -2 frames. if the microprocessor interface is not being used for controlling the c/i channel, commands have to be applied continuously on din until the command is validated by the iec-q and the desired action has been initiated. afterwards the command may be changed which would initiate another action by the iec-q. an indication is issued permanently by the iec-q on dout until a new indication needs to be forwarded. in stand-alone mode the active c/i channel is controlled by an external device, e.g. the icc, 3pac, ipac or isar, epic ? , elic ? . in p mode the active c/i channel can either be controlled by an external device or via the microprocessor interface. for a description on how to access the active c/i channel via the p-interface please refer to chapter "microprocessor access to iom ? -2 channels", page 97. all available c/i codes of the iec-q are listed and explained in "c/i channel codes", page 224. du 1 1 bac tba2 tba1 tba0 1 1 dd ees/ga/b1111 peb 2091 pef 2091 functional description semiconductor group 76 data sheet 01.99 3.6.2.2 c/i channel 1 c/i channel 1 (c/i1) is only available in te mode (dcl = 1.536 mhz). the channel consists of six bits in each direction. in stand-alone mode the c/i1 channel is ignored by the u transceiver. in p mode it can be accessed via registers ciwi/u and ciri/u (see "c/i channel access", page 100). 3.6.3 iom ? -2 monitor channel the monitor channel protocol is a full duplex handshake protocol used for programming and monitoring devices in the active monitor channel or on monitor channel 1 in the te mode. these can include the iec-q itself as well as external devices connected to the iom ? -2 interface. the monitor channel consists of 8 bits, located at position 17-24 of every time slot. for handshake control bits mr and mx at positions 31 and 32 of every time slot are used (see figure 24, page 71). 3.6.3.1 active monitor channel the active monitor channel is available in all operational modes. the iec-q is always controlled and monitored via active monitor channel. in stand-alone mode the monitor channel is controlled by an external device, e.g. the icc, 3pac, ipac or isar, epic ? , elic ? . in p mode the monitor channel can either be controlled by an external device or via the microprocessor interface. for a description on how to access the active monitor channel via the p-interface please refer to "monitor channel access", page 101. structure of monitor messages monitor messages sent to the iec-q are always 2 bytes long, monitor messages returned by the iec-q are 2 or 4 bytes long depending on the command. 4 byte long return messages (internal register data) are issued via 2 messages containing 2 bytes each. table 11 below shows the general structure of 2 bytes monitor messages. table 11 general monitor channel structure 1. byte 2. byte a3 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address data data data peb 2091 pef 2091 functional description semiconductor group 77 data sheet 01.99 the first four bits of this two byte message gives the address of the monitor message. this address defines the type of the monitor message. example : a monitor message with an address 0 h , i.e. address= 0000 will be called mon-0 message. a monitor message with an address 8 h , i.e. address= 1000 will be called mon-8 message. the iec-q will respond only to mon-0, mon-1, mon-2 and mon-8 messages in the active channel. all other messages will be ignored. the 12 bits d0-d11 of a monitor message will have different meanings, depending on message type and on the function used. an overview of monitor channel commands and indications of the iec-q are listed in section 6.2, page 226. priority in the receive direction monitor channel commands (given to the iec-q) will be handled sequentially. in the transmit direction messages will be handled according to the following priority if several of them are pending (to be issued by the iec-q): mon-0 will have the first priority and will be therefore issued first. mon-1 will have the second, mon-2 the third and mon-8 the last priority. however, an already running message will not be aborted, even if a higher priority message is pending. verification the monitor message on din is considered valid only if it consists of exactly two bytes. longer messages or single-byte messages will be discarded. a double last-look criterion is implemented for both bytes of the monitor message. if the received bytes are not identical in the first two received frames the message will be aborted. handshake procedure figure 28 illustrates a monitor channel transfer of a 2-byte monitor command followed by a 2-byte iec-q-response. this requires a minimum of 15 iom ? -2 frames (reception 7 frames + transmission 8 frames = 1.875 ms). in case the controller is able to confirm the receipt of first iec-q-response byte in the frame immediately following the mx-transition on dout from high to low (i.e. in frame no. 9), 1 byte may be saved 1) (7 frames + 7 frames). note 16: transmission and reception of monitor messages can be performed simultaneously by the iec-q. in the procedure depicted in figure 28 it would be possible for the iec-q to transmit monitor data in frames 1C5 (excluding eom-indication) and receive monitor data from frame 8 onwards. 1) this is referred to as the "fast handshake" peb 2091 pef 2091 functional description semiconductor group 78 data sheet 01.99 m 1/2:monitor message 1. and 2. byte r 1/2:monitor response 1. and 2. byte eom: end of message: mx=1 and mr=1 in two consecutive iom ? -2-frames. figure 28 handshake protocol with a 2-byte monitor message/response idle state after the bits mr and mx have been held inactive (i.e. high) for two or more successive iom ? -2-frames, the channel is considered idle in this direction. transmission abortion if no eom is detected after the first two monitor bytes, or received bytes are not identical in the first two received frames, transmission will be aborted through receiver by setting the mr-bit inactive for two or more iom ? -2-frames. the controller reacts with eom. this situation is illustrated in figure 29 below. r iom -2 frame 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ff ff ff ff ff ff ff ff ff ff ff m2 2 m 1 m 1 m din 0 1 0 1 mr mx dout 0 1 0 1 mr mx mon. r1 r1 r2 2 r ff ff ff ff ff ff ff ff ff ff r1 dout din tx 1.byte 2.byte tx ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 1.byte ack. ack. 2.byte 1.byte tx tx 2.byte 2.byte ack. ack. 1.byte eom itd04230 data mon. data eom eom no. eom peb 2091 pef 2091 functional description semiconductor group 79 data sheet 01.99 figure 29 abortion of monitor channel transmission example: standard transmission procedure in stand-alone mode 1. the first byte of monitor data is placed by the external controller (e.g. icc, epic ? ) on the din line of the iec-q and mx is activated (low; frame no. 1). 2. the iec-q reads the data of the monitor channel and acknowledges by setting the mr-bit of dout active if the transmitted bytes are identical in two received frames (frame no. 2 because the iec-q reads and compares data already while the mx-bit is not activated). 3. the second byte of monitor data is placed by the controller on din and the mx-bit is set inactive for one single iom ? -2-frame. this is performed at a time convenient to the controller. 4. the iec-q reads the new data byte in the monitor channel after the rising edge of mx has been detected. in the frame immediately following the mx-transition active-to-inactive, the mr-bit of dout is set inactive. the mr-transition inactive-to-active exactly one iom ? -2-frame later is regarded as acknowledgment by the external controller (frame no. 4C5). the acknowledgment by the iec-q will always be sent two iom ? -2-frames after the activation of a new data byte. 5. after both monitor data bytes have been transferred to the iec-q, the controller transmits "end of message" (eom) by setting the mx-bit inactive for two or more iom ? -2-frames (frame no. 5C6). 6. in the frame following the transition of the mx-bit from active to inactive, the iec-q sets the mr-bit inactive (as was the case in step 4). as it detects eom, it keeps the mr-bit inactive (frame no. 6). the transmission of the monitor command by the controller is complete. 7. if the iec-q is requested to return an answer it will commence with the response as soon as possible. in case the "monitor time-out" function is enabled it may have to itd04231 mx mr mx mr eom 1234567 abort request from receiver 1 0 1 0 1 0 1 0 din dout frame no. r iom -2 peb 2091 pef 2091 functional description semiconductor group 80 data sheet 01.99 postpone the answer until after the internal reset, see "monitor procedure time-out (mto)", page 55. figure 28, page 78 illustrates the case where the response can be sent immediately. the procedure for the response is similar to that described in points 1 C 6 except for the transmission direction. it is assumed that the controller does not latch monitor data. for this reason one additional frame will be required for acknowledgment. transmission of the 2nd monitor byte will be started by the iec-q in the frame immediately following the acknowledgment of the first byte. the iec-q does not delay the monitor transfer. 3.6.3.2 monitor channel 1 monitor channel 1 is only available in te mode (dcl = 1.536 mhz). in stand-alone mode the monitor 1 channel is ignored by the iec-q. in p mode it can be accessed via the microprocessor interface to control an external device (e.g. sicofi ? , arcofi ? ). for a detailed description of the microprocessor interface access to the monitor channel see "monitor channel access", page 101. 3.6.3.3 monitor procedure time-out note 17: this feature is only available for the active monitor channel, see "active monitor channel", page 76. the iec-q can operate with or without the "monitor procedure time-out" feature. for mode setting see "monitor procedure time-out (mto)", page 55. with the mto-function enabled, the monitor routine is reset twice per u-superframe (see "u -frame structure", page 67 for definition). the resets are performed at the start of the first and 49th iom ? -2-frame (see figure 30). every reset sets both handshake bits of dout to the idle state (mr and mx set to high) thereby preventing lock-up situations. monitor channel transmitter and receiver are reset synchronously. with the mto-function disabled no internal resets are performed. this eliminates the restrictions described in the following paragraphs, requires however an external controller to prevent lock-up situations in the monitor channel. peb 2091 pef 2091 functional description semiconductor group 81 data sheet 01.99 figure 30 monitor access with mto enabled monitor channel transmitter and mto enabled the transmitter is reset in 6 ms intervals in the frames shown above. in case the transmission of a monitor message has not been completed before the transmitter is reset, the complete message will be lost. a message that has been lost due to the interruption of a monitor reset will not be retransmitted. to prevent this loss of monitor messages, the iec-q will only commence a monitor transmission if more than 16 iom ? -2 frames will be available for transmission before the next reset occurs. transmission thus does not start during frame numbers 33 48 and 81 96. to ensure correct transmission the receiver must not delay the receive procedure for more than the following value: ? 2-byte transmission: max. speed = 8 frames => max. controller (receive) delay = 8frames. monitor channel receiver and mto enabled the receiver is reset in 6 ms intervals in the frames shown above. in case the reception of a monitor message has not been completed before the receiver is reset, the complete message can be lost because the generation of an abort request can not be guaranteed. to prevent this loss of monitor messages the peb 2091 will only commence a monitor reception (i.e. acknowledge the 1st received byte) if more than 16 iom ? -2 frames will be available for reception before the next reset occurs. reception thus does not start during frame numbers 33 48 and 81 96. to ensure correct reception, the transmitter must not delay the receive procedure for more than the following value: ? 2-byte reception: max. speed = 7 frames => max. controller (transmit) delay = 9 frames. itd04232 superframe 1isw23456781 12 24 36 48 60 72 84 96 no start of new transfer 132 reset reset 80 49 start of no new transfer receive u frame superframe marker frame possible start of monitor procedure r iom peb 2091 pef 2091 functional description semiconductor group 82 data sheet 01.99 3.6.4 activation/deactivation of iom ? -2 clocks note 18: this section applies only in the nt, nt-auto activation, nt-rp and te modes. the iom ? -2 clocks may be switched off if the iec-q is in state deactivated (see "state machine in nt modes", page 160). this reduces power consumption to a minimum. in this deactivated state the clock lines are low and the data lines are high. the power-down condition within the deactivated state will only be entered if no monitor messages are pending on iom ? -2. for information on how to keep the iom ? -2 clocks active in all states please refer to the application note providing clocks in deactivated state. the deactivation procedure is shown in figure 31. after detecting the code di (deactivation indication) the iec-q responds by transmitting dc (deactivation confirmation) during subsequent frames and stops the timing signals after the fourth frame. figure 31 deactivation of the iom ? -2 clocks the iom ? -2 clocks are activated automatically when one of the following conditions apply ? the din line is pulled low itd10292 di di di di di di fsc din dout dc dc dc dc dr dr detail see fig.b din dcl dc/ ii / c i / c i / c deactivated deactivated a) b) r iom -2 interface iom -2 interface r peb 2091 pef 2091 functional description semiconductor group 83 data sheet 01.99 ? the bit ciwu:spu is set to 0 or ? a wake-up tone is detected on the u-interface dcl is activated such that its first rising edge occurs with the beginning of the bit following the c/i0 channel. after the clocks have been enabled this is indicated by the pu code in the c/i0 channel. for detailed operational description, see "state machine in nt modes", page 160 ff. 3.7 clocks clock generation of the iec-q depends on the mode used. the following sections will describe the properties of these clocks in each mode. for better understanding of the clock scheme in the different applications the properties of the iom ? -2 clocks will also be outlined. peb 2091 pef 2091 functional description semiconductor group 84 data sheet 01.99 3.7.1 lt mode figure 32 clock generation for lt mode the lt mode is typically chosen for isdn-line card applications. the u transceiver has to synchronize onto an externally provided ptt-master clock. a phase locked loop (pll) is required to generate the iom ? -2 clock signals fsc (frame synchronization) and dcl (data clock) as well as the 15.36 mhz iec-q master clock. xin/xout pin xout should be left open. the synchronized 15.36 mhz clock should be provided on pin xin. a synchronized iec-q system clock guarantees that u-interface transmission will be synchronous to the ptt-master clock. 15.36 mhz 512-4096 khz 8 khz pll % ptt ref. clock ( downstream ) synchr. lt xin fsc dcl u interface lt xin dcl u interface lt xin u interface fsc fsc dcl 1 2 8 peb 2091 pef 2091 functional description semiconductor group 85 data sheet 01.99 the dynamic characteristics of this clock are described in "lt modes", page 281. clock cls this clock is not defined in this mode. 3.7.2 nt and te mode in nt and te modes the iec-q recovers the timing directly from the u-interface. synchronization to the u-interface is achieved by including correction steps in the divider of the 15.36-mhz base clock. thus the issued iom ? -2 clock signals are synchronous to the ptt-master clock on lt side. xin/xout a free running crystal or other clock source should provide a 15.36-mhz base clock (see also external circuitry on page 249 for more informations about crystal properties). cls clock in these modes the iec-q issues a 7.68-mhz clock signal. this clock signal is synchronous to the received u-interface signal. in order to achieve synchronism the free running 15.36-mhz master clock is not permanently divided by 2. adjustment steps are included by division with 1 or 3. it is not available in power down. figure 33 clock in nt mode nt cls=7680 khz xin xout u interface fsc=8 khz dcl=512 khz (downstream) synchr. figure 33 clocks in te mode te cls=7680 khz xin xout u interface fsc=8 khz dcl=1536 khz (downstream) synchr. peb 2091 pef 2091 functional description semiconductor group 86 data sheet 01.99 3.7.3 nt-pbx figure 34 clock generation in nt-pbx mode in nt-pbx mode iom ? -2 clock signals are not issued by the device but need to be generated externally. in order to ensure synchronous timing to the ptt-master clock, a pll is used for generation of fsc and dcl (supplied to nt-pbx and lt devices) as well as of the 15.36-mhz system clock (lt only). pll 512 khz 15.36 mhz 512-4096 khz % nt-pbx xin xout u interface lt xin fsc dcl u interface nt-pbx cls u interface lt xin fsc dcl u interface nt-pbx cls u interface lt xin fsc dcl u interface 8 khz fsc dcl dcl fsc fsc dcl 1 2 88 2 1 512 khz 512 khz cls (reference clock) (downstream) synchr. (downstream) synchr. cls peb 2091 pef 2091 functional description semiconductor group 87 data sheet 01.99 note 19: it may be necessary to use a multiplexer for the pll-reference clock because the cls-signal is available only if the corresponding line is active. if the referenced line is not active the pll must be supplied by the cls of another active iec-q of the pbx. xin/xout a free running crystal or other clock source should provide a 15.36-mhz base clock (see also "external circuitry", page 249 for more informations about crystal properties). cls a 512 khz clock synchronous to the ptt is provided. this clock should be used as the reference clock for the pll. it is not available in power down. 3.7.4 repeater modes figure 35 clock generation in repeater mode in repeater applications the nt repeater issues iom ? -2 clocks for direct use in the lt repeater. the lt repeater is synchronized to the upstream unit through the nt repeater. to achieve this, a pll is required to provide a synchronized 15.36 mhz master clock to the lt repeater. lt-rp pll xin fsc 15.36 mhz 15.36 mhz dcl cls dcl 512 khz u interface nt-rp cls xin xout u interface (downstream) synchr. (downstream) synchr. peb 2091 pef 2091 functional description semiconductor group 88 data sheet 01.99 3.7.4.1 nt repeater xin/xout a free running crystal or other clock source shall provide a 15.36-mhz base clock (see also "external circuitry", page 249 for more informations about crystal properties). cls in this mode version 5.3 provides an unsychronized 15.36 mhz clock on cls. this clock can be used by the pll as a base clock. it is also available in power down. 3.7.4.2 lt repeater xin/xout pin xout should be left open. the synchronized 15.36 mhz clock should be provided on pin xin. the dynamic characteristics of this clock are described in "lt modes", page 281. clock cls in this mode a 512 khz clock is provided on cls. this clock signal is not synchronous to the received u-interface signal. it is also available in power down. 3.7.5 cot-512 and cot-1536 mode because pair gain systems do not need to synchronize onto a ptt-master clock, a free running 15.36-mhz system clock may be used at the exchange side. in cot mode the figure 36 clocks in cot-512 mode cot-512 cls=7680 khz xin xout u interface fsc=8 khz dcl=512 khz figure 36 clocks in cot-1536 mode cot-1536 cls=7680 khz fsc=8 khz dcl=1536 khz u interface xin xout peb 2091 pef 2091 functional description semiconductor group 89 data sheet 01.99 iec-q issues all iom ? -2 clocks. an external clock generation circuit is not required. information on the u-interface is transmitted synchronous to the system clock. xin/xout a free running crystal or other clock source should provide a 15.36-mhz base clock (see also external circuitry on page 249 for more informations about crystal properties). cls clock in these modes the iec-q issues a 7.68-mhz clock signal. this clock signal is not synchronous to the received u-interface signal. it is also available in power down. 3.7.6 microprocessor clock output note 20: this clock is only available in the p mode. the microprocessor clock on the mclk-output. four clock rates are provided by a programmable prescaler in the adf register (see "adf-register", page 219). these are 7.68 mhz, 3.84 mhz, 1.92 mhz and 0.96 mhz. the default value after reset is 3.84 mhz. switching between the clock rates is realized without spikes. the oscillator remains active all the time. the clock is synchronized to the 15.36 mhz clock at the xin pin. peb 2091 pef 2091 functional description semiconductor group 90 data sheet 01.99 3.8 microprocessor interface note 21: this interface is only available in the microprocessor mode. the parallel/serial microprocessor interface can be selected to be either of the 1. siemens/intel non-multiplexed bus type with control signals cs , wr , rd 2. motorola type with control signals cs , r/w , ds 3. siemens/intel multiplexed address/data bus type with control signals cs , wr , rd , ale 4. serial mode using control signals cdin, cdout, cclk and cs . the selection is performed via pins ale/cclk and smode as follows: the occurrence of an edge on ale/cclk, either positive or negative, at any time during the operation immediately selects interface type 3 or 4. a return to one of the other interface types is possible only if a hardware reset is issued. the timing of the different microprocessor bus types is given in sections 8.7.1, page 269 for the parallel bus type and in section 8.7.2, page 273, for the serial bus type. 3.9 s/g bit and bac bit control note 22: this chapter applies only in the p-te mode (see "basic operating mode", page 50). if dcl = 1.536 mhz the iom ? -2 interface consists of three iom ? -2 channels (see "terminal timing mode", page 73). the last octet of an iom ? -2 frame includes the s/g and the bac bit. either or both bits can be used in various applications including ? the d-channel arbitration in a pbx via an elic ? on the line card ? the synchronization of a base station in wireless local loop applications the s/g bit is always written and never read by the iec-q. its value depends on the last received eoc-command and on the status of the bac bit. the processing mode for the s/g bit is selected via bits swst:bs, swst:sgl and adf:cbac (see "adf-register", page 219). a detailed operational description of the s/g bit control in all modes is provided in "s/g bit and bac bit operations", page 198. table 12 microprocessor interface modes ale smode siemens/intel non-mux 0 x motorola 1 x siemens/intel mux edge 0 serial edge 1 peb 2091 pef 2091 functional description semiconductor group 91 data sheet 01.99 s/g status indication on pin sg if one of the packages m-qfp-64 or t-qfp-64 is being used the s/g bit status information will be additionally provided on pin sg, see "miscellaneous function pins", page 46. this feature is not available in the package p-lcc-44. 3.10 power controller interface note 23: this chapter applies only in stand-alone mode. a power controller interface is implemented in the iec-q to provide comfortable access to peripheral circuits which are not connected directly to the microprocessor. because this interface was specifically designed to support the isdn exchange power controller iepc (peb 2025) it is referred to as "power controller interface". despite this dedication to the iepc, the controller interface is just as suited for other general-purpose applications. the interface structure consists of C 3 bit data bus pcd0 ... 2 C 2 bit address bus pca0,1 C 3 control signals pcrd and pcwr C 1 interrupt facility int see also "power controller pins", page 36, for information about pin configurations. the address bits are latched, they may therefore in general interface applications be used as output lines. for general interface inputs each of the three data bits is suitable. read and write operations are performed via mon-8 commands. three inputs and two outputs are thus available to connect external circuitry. the interrupt pin is edge sensitive. each change of level at the pin int will initiate a c/i-code int lasting for four iom ? -2-frames. interpretation of the interrupt cause and resulting actions need to be performed by the control unit. for informations about communication with the power controller interface, see "access to power controller interface", page 196. for informations about dynamic characteristics of the power controller interface, see "power controller interface timing", page 277. peb 2091 pef 2091 functional description semiconductor group 92 data sheet 01.99 3.11 power status two pins ps1 and ps2 are available for comfortably surveying and controlling the power status. in addition, if the stand-alone mode is being used, a third pin (diss) is also available. in nt mode, power status bits 1 and 2 (ps1/2) are used to monitor both primary and secondary nt power supply. this information is transferred via the overhead bit channel to the exchange side. for operational details, see "monitoring primary and secondary nt power supply", page 194. in lt mode the first power status bit (ps1) is used to monitor the remote power feed circuit of the subscriber line. for operational details, see "monitoring remote power feed circuit in lt modes", page 194. the pin ps2 provides a serial interface in order to read in the value of the current fed to the subscriber line by the power controller. this function is available only in combination with a power controller which supports this feature (the iepc does not). for operational details, see "monitoring power feed current in lt modes", page 194. if the stand-alone mode is being used the following features are also available. in the nt and te modes the output pin disable (diss) is set to (1) if the eoc-command "close complete loop" (lbbd) has been detected by the nt. this function is only available in eoc auto mode. it may be used to test a secondary power source (e.g. battery check). for operational details, see "access to pin diss", page 195. in the lt modes the diss-pin is used for switching off the remote power supply of the subscriber line. for operational details, see "access to pin diss", page 195. 3.12 undervoltage detection note 24: this chapter applies only in the microprocessor mode (pmode = "1"). the undervoltage detector is enabled by setting the adf:uvd bit to "1", see "adf-register", page 219. note that the default setting of this bit after power on will be "1", i.e. the undervoltage detection feature will be activated. it activates the reset signal if the supply voltage drops below the threshold u l (typically 4.21 v, see figure 37 below and "undervoltage detection timing", page 280). it also acts as power on reset by creating a reset pulse on pin rst if the supply voltage rises above u h (typically 4.30 v). it then stays inactive until the supply voltage drops again below the threshold level u l (see also "power on reset (por)", page 93, for more information). peb 2091 pef 2091 functional description semiconductor group 93 data sheet 01.99 figure 37 uvd control of pin rst while the supply voltage is below threshold u l , the microcontroller clock mclk is stopped and the mclk output remains low 1) . if the supply voltage falls below threshold u l , the clock is stopped immediately which may result in one shorter high period of the clock signal. note 25: for power saving reasons, this function is not available in power down. still pin rst will not float in this state and the power on reset function is still available, see 3.14 below. 3.13 watchdog timer note 26: this chapter applies only in the microprocessor mode (pmode = "1"). the watchdog is enabled by setting the swst:wt bit to "1", see "swst-register", page 220. the value of swst:wt after hardware reset (res = 0) is "0". after the microcontroller has enabled the watchdog timer it has to write the bit patterns "10" and "01" in adf:wtc1 and adf:wtc2 within a period of 132 ms, see "adf-register", page 219. if it fails to do so, a reset signal of 5 ms at pin rst is generated. the clock at pin mclk remains active during this reset. 3.14 power on reset (por) the peb/f 2091 is equipped with a por feature. during power on or power off, an internal reset will be generated if the por threshold (between 2.5 v and 4.5 v) is 1) the behavior of the microcontroller clock mclk is not specified below the supply voltage of 4.0 volt. u h rst vdd u l 1.0v peb 2091 pef 2091 functional description semiconductor group 94 data sheet 01.99 reached. this is independent of mode setting. however there is a difference in reset duration and indication between the stand-alone mode and the microprocessor mode. in stand-alone mode this internal reset (por) will be fully equivalent to the hardware reset generated by activating the pin res . the duration of the reset pulse will be some value between 10 and 30 s. the processor mode (pmode="1") has two additional properties: - the por will be given on the pin rst - the por will also reset the register stcr. see "stcr-register", page 212. the duration of por in this mode will be some value between 60 and 70 ms. 3.15 reset behavior several resets are provided in the iec-q (see chapters 3.12, 3.13 and 3.14 above). their effects are summarized in table 13. definition the transceiver core is said to be reset if the receiver coefficients, the awake unit, the monitor channel procedure and the state machine are reset. table 13 reset reset condition effect pin rst active 1) 1) applies only in the microprocessor mode power-on power-on resets the transceiver core 2) . resets all registers in the microprocessor mode 2) in all iom ? -2 slave modes this reset will be carried out only after the iom ? -2 clocks has been applied to the iec-q yes uvd power supply drop resets the transceiver core 2) . resets all registers in the microprocessor mode yes hardware reset pin res = 0 resets the transceiver core 2) . resets all registers except for register stcr in the microprocessor mode no watchdog watchdog expired no internal effect yes software reset c/i = 0001 resets the transceiver core no peb 2091 pef 2091 functional description semiconductor group 95 data sheet 01.99 the clock mclk is delivered during reset (except for power-on and undervoltage detection). table 13 shows that the output pin rst is controlled by power-on reset, undervoltage detection and the watchdog timer. figure 38 illustrates the reset sources that have an impact on pin rst . figure 38 reset sources 3.16 test block in stand-alone mode the two pins tp and tp1 are used for internal manufacturing device tests. in microprocessor mode only pin tp is used for device test. test pins are not defined for normal system operation, as described in this document, and should therefore be left unconnected. undervoltage detection power-on reset watchdog + 67 ms 60-70 ms 5 ms rst peb 2091 pef 2091 operational description semiconductor group 96 data sheet 01.99 4 operational description in chapters 2 and 3 the pins and users interfaces of the iec-q are described in detail. using this information, this chapter describes the interaction between these interfaces in detail. the approach used is to describe how iec-q features can be accessed using the different user interfaces, described in chapter 3. most of the iec-q features can be accessed via iom ? -2 interface. in the microprocessor mode the processor interface provides almost unlimited access to the iom ? -2 channels in upstream and downstream directions, and consequently to most of the iec-q features. this p access to the iom ? -2 interface is described in section 4.1. access to the u-interface is the scope of section 4.2. a detailed description is given about the possibilities of (always indirect) access to each channel of the u-interface and the behavior of the iec-q in each mode (e.g. nt, lt, eoc auto and transparent modes). sections 4.3 and 4.4 cover the whole issue of activation and deactivation procedures and control. section 4.3 describes layer 1 activation and deactivation procedures of different configurations. section 4.4 describes the activation and deactivation control of the different modes of the iec-q itself. access to numerous maintenance features is discussed in sections 4.5 through 4.9. this includes monitoring transmission quality, features supporting test loop-backs defined by the national ptts, power status monitoring features as well as chip internal testing features. features of the power controller interface are described in section 4.10 which applies only in the stand-alone mode. section 4.11 applies only to the microprocessor mode if used in the nt or the te mode, and describes how to program and access the s/g and bac bit features which can be used in applications like wireless local loop and d-channel arbitration. peb 2091 pef 2091 operational description semiconductor group 97 data sheet 01.99 4.1 microprocessor access to iom ? -2 channels note 27: this chapter applies only in p mode. in p mode the microcontroller has access to the iom ? -2 channels via the processor interface (pi) and registers. figure 39 access to iom ? -2 channels (p mode) the processor interface can be understood as an intelligent switch between iom ? -2 and the transceiver core. it handles d, b1, b2, c/i and monitor-channel data. the data can either be transferred directly between iom ? -2 and the transceiver core, or be controlled via the pi. the pi acts as an additional participant to the monitor channel. switching directions are selected by setting the register swst as indicated below: ? setting one of the 5 bits b1, b2, d, ci, or mon of swst to "1" enables the p access to the corresponding data. ? setting the bits listed above to "0" directly passes the corresponding data from iom ? -2 to the transceiver core and vice versa. refer also to "swst-register", page 220 for more details. the default value after hardware reset is "0" at all 8 positions. swst-register wt b1 b2 d ci mon bs sgl its10193 fsc pi u u r iom -2 - 2 peb 2091 pef 2091 operational description semiconductor group 98 data sheet 01.99 note 28: the microprocessor interface provides almost unlimited access possibilities to the active iom ? -2 channel. one important consequence is that all actions described in this document involving the active channel of the iom ? -2 interface or parts of it (e.g. b, d, monitor and c/i channels) can be also performed using the pi. in the iom ? -2 master mode proper function using the microprocessor interface is possible even if the iom ? -2 interface is omitted. in this case pin din should be clamped to 1. in the iom ? -2 slave mode the iom ? -2 clocks can not be omitted. they are needed for internal data synchronization reasons. if pin din is not used, it should be clamped to 1. if pin dout is not used it should be left open. 4.1.1 b-channel access setting swst:b1 (b2) to "1" enables the microprocessor to access b1 (b2)-channel data between iom ? -2 and the transceiver core. eight registers (see table 14) handle the transfer of data from iom ? -2 to the p, from the p to iom ? -2, from the p to transceiver core and from transceiver core to the p: for more informations about these registers, refer to "b-channel access registers", page 221. every time b-channel bytes arrive, an interrupt ista:b1 or ista:b2 respectively is created. it is cleared after the corresponding registers have been read. ista:b1 is cleared after rb1u and rb1i have been read. ista:b2 is cleared after rb2i and rb2u have been read. after an interrupt the data in rb1u and rb1i is stable for 125s. for more informations, refer to "interrupt structure", page 209. table 14 b1/b2-channel data registers register function wb1u write b1-channel data to transceiver core rb1u read b1-channel data from transceiver core wb1i write b1-channel data to iom ? -2 rb1i read b1-channel data from iom ? -2 wb2u write b2-channel data to transceiver core rb2u read b2-channel data from transceiver core wb2i write b2-channel data to iom ? -2 rb2i read b2-channel data from iom ? -2 peb 2091 pef 2091 operational description semiconductor group 99 data sheet 01.99 4.1.2 d-channel access setting swst:d to "1" enables the microprocessor to access d-channel data between the iom ? -2 and the transceiver core. four registers (see table 15) handle the transfer of data from iom ? -2 to the p, from the p to iom ? -2, from the p to transceiver core and from transceiver core to the p. see "d-channel access registers", page 221 for more details about these registers. . two 2-bit fifos of length 4 collect the incoming d-channel packets from iom ? -2 and u. every fourth iom ? -2-frame when they are filled, an interrupt ista:d is generated and the contents of the fifos are shifted in parallel to dru and dri respectively. dru and dri have to be read before the next interrupt ista:d can occur, otherwise 8 bits will be lost. dwu and dwi have to be loaded with data for 4 iom ? -2-frames. data in dwu and dwi is assumed to be valid at the time ista:d occurs (see also "interrupt structure", page 209). the register contents are shifted in parallel into two 2-bit fifos of length four, from where the data is put to iom ? -2 and transceiver core respectively during the following 4 iom ? -2-frames. during this time, new data can be placed on dwu and dwi. dwu and dwi are not cleared after the data was passed to the fifos. that is, a byte may be put into dwu or dwi once and continuously passed to iom ? -2 or transceiver core, respectively. figure 40 illustrates this procedure: figure 40 procedure for the d-channel processing note 29: default of dwu, dwi, dru and dri after reset is "ff h ". table 15 d-channel data registers register function dwu write d-channel data to transceiver core dru read d-channel data from transceiver core dwi write d-channel data to iom ? -2 dri read d-channel data from iom ? -2 itd08120 2 bits dru or dri dwu or dwi leaving d-channel bits arriving d-channel bits peb 2091 pef 2091 operational description semiconductor group 100 data sheet 01.99 4.1.3 c/i channel access setting swst:ci to "1" enables the microprocessor to access c/i-commands and indications between iom ? -2 and the transceiver core. a change in two consecutive frames (double last look) in the c/i-channel on iom ? -2 is indicated by an interrupt ista:cici. the received c/i-command can be read from register ciri. a change in the c/i-channel coming from the transceiver core is indicated by an interrupt ista:cicu. the new c/i-indication can be read from register ciru. note 30: the term c/i-indication always refers to a c/i-code coming from the transceiver core, whereas the term c/i-command refers to a c/i-code going into the transceiver core. a c/i-code going to the transceiver core has to be written into the ciwu-register. a c/i-code to iom ? -2 has to be written into the ciwi-register. the contents of both registers (ciwu and ciwi) will be transferred at the next available iom ? -2 frame. the registers are not cleared after the transfer. therefore, it is possible to continuously send c/i codes to iom ? -2 or the transceiver core by only writing the code into the register once. c/i-commands to the transceiver core have to be applied at least for two iom ? -2 frames (250 s) to be considered as valid. for more information see section 5.2.7, page 217 and thereafter. see also "interrupt structure", page 209. in te mode (i.e. 1.536 mhz dcl), the adf2:te1 bit is used to direct the c/i-channel access either to iom ? -2 channel 0 (adf2:te1 = 0, default) or to iom ? -2 channel 1 of the iom ? -2 terminal structure (adf2:te1 = 1), see figure 41. this allows to program terminal devices such as the arcofi ? via the processor interface of the iec-q. the c/i code going to iom ? -2 is 4 bits long if it is written to iom ? -2 channel 0 (adf2:te1 = 0). if written to iom ? -2 channel 1 this c/i code is 6 bits long (adf2:te1 = 1). if the adf2:te1 bit is 1, the c/i channel on iom ? -2 channel 0 is passed transparently from the iom ? -2 interface to the transceiver core. see also "adf2-register", page 214 for more information about this register. peb 2091 pef 2091 operational description semiconductor group 101 data sheet 01.99 figure 41 c/i channel access 4.1.4 monitor channel access setting swst:mon to "1" enables the microprocessor to access monitor-channel messages at iom ? -2 interface and the transceiver core. monitor-channel access can be performed in three different iom ? -2 channels (see figure 42). itb10296 adf2 : te1 = 1 swst : ci = 1 iec-q core c/i access to iom -2 channel 1 r ciwu ciru ciwi ciri c/i 1 (6 bit) iom -2 r itb10295 adf2 : te1 = 0 swst : ci = 1 iec-q core c/i access to iom -2 channel 0 r ciwu ciru ciwi ciri c/i 0 (4 bit) iom -2 r (4 bit) c/i peb 2091 pef 2091 operational description semiconductor group 102 data sheet 01.99 figure 42 monitor channel access directions setting swst:mon to 0 disables the controller access to the monitor channel (figure 42 upper left part). setting swst:mon to 1 enables three different ways of controller access to the monitor channel. adf2:te1 set to 0 allows to access either the transceiver core of the iec-q (see figure 42 upper right part, adf2:min = 1) or the iom ? -2 interface of the iec-q (figure 42 lower left part, adf2:min = 0). setting adf2:te1 to 1 in te mode gives access to iom ? -2 channel 1 rather than iom ? -2 channel 0 directed out of the iec-q. this allows to program devices linked to iom ? -2 channel 1 (e.g. arcofi ? ) via the processor interface of the iec-q. its10293 "din" "dout" iec-q core iec-q te p interface m swst : mon = 0 din dout dout din adf2 : te1 = 0 adf2 : min = 1 swst : mon = 1 m p interface iec-q te iec-q core "dout" "din" mode 1 : monitor channel access disabled to kernel "din" "dout" iec-q core iec-q te p interface m swst : mon = 1 adf2 : min = x adf2 : te1 = 1 din dout dout din adf2 : te1 = 0 adf2 : min = 0 swst : mon = 1 m p interface iec-q te iec-q core "dout" "din" to iom -2 mode 2 : monitor channel access mode 3b : monitor channel access mode 3a : monitor channel access to iom -2 channel 1 in te mode iom -2 channel 1 r r r iom -2 channel 0 r peb 2091 pef 2091 operational description semiconductor group 103 data sheet 01.99 4.1.4.1 monitor channel protocol the pi allows to program the iec-q monitor channel in the way known from the peb 2070 (icc). the monitor channel operates on an asynchronous basis. while data transfers on the iom ? -2-bus occur synchronized to frame sync fsc, the flow of data is controlled by a handshake procedure using the monitor channel receive (mr) and monitor channel transmit (mx) bits. for example: data is placed onto the monitor channel and the mx bit is activated. this data will be transmitted repeatedly once per 8-khz frame until the transfer is acknowledged via the mr bit. the microprocessor may either enforce a "1" (idle) in mr, mx by setting the control bit mocr:mrc or mocr:mxc to "0", or enable the control of these bits internally by the iec-q according to the monitor channel protocol. thus, before a data exchange can begin, the control bits mrc or mxc should be set to "1" by the microprocessor. the monitor channel protocol is illustrated in figure 43. the relevant control and status bits for transmission and reception are: table 16 monitor transmit bits register bit control / status function mocr mxc control mx bit control mxe transmit interrupt enable mosr mda status data acknowledged mab data abort star mac transmission active table 17 monitor receive bits register bit control / status function mocr mrc control mr bit control mre receive interrupt enable mosr mdr status data received mer end of reception peb 2091 pef 2091 operational description semiconductor group 104 data sheet 01.99 figure 43 monitor channel protocol before starting a transmission, the microprocessor should verify that the transmitter is inactive, i.e. that a possible previous transmission has been terminated. this is indicated by a "0" in mosr:mac, the monitor channel active status bit. to enable interrupts for the transmitter the mocr:mxe bit must be set to "1" (for details see "monitor-channel interrupt logic", page 209). after having written the monitor data transmit (mox) register, the microprocessor sets the monitor transmit control bit mxc to "1". this enables the mx bit to go active ("0"), indicating the presence of valid monitor data (contents of mox) in the corresponding frame. as a result, the receiving device stores the monitor byte in its monitor receive (mor) register and generates an mdr interrupt status. itd08119 mon mx transmitter mr 1 1 ff ff 1 1 adr 0 1 0 0 data1 0 1 data1 adr 0 0 data1 0 1 data1 0 0 0 0 data2 0 1 data2 data2 0 1 data2 0 0 ff 1 0 ff 1 0 ff 1 1 ff 1 1 receiver mxe = 1 adr = mox mxc = 1 1 = mac mox = data1 mda int. mda int. data2 = mox mda int. 0 = mxc 0 = mac mdr int. rd mrc mor =1 (= adr) data1) (= mor rd mdr int. mdr int. rd mor (= data2) mrc = 0 mer int. 125 m s m p p m 1 mre = peb 2091 pef 2091 operational description semiconductor group 105 data sheet 01.99 alerted by the mdr interrupt, the microprocessor reads the monitor receive (mor) register. when it is ready to accept data (e.g. based on the value in mor, which in a point-to-multipoint application might be the address of the destination device), it sets the mr control bit mrc to "1" to enable the receiver to store succeeding monitor channel bytes and acknowledge them according to the monitor channel protocol. in addition, it enables other monitor channel interrupts by setting monitor receive interrupt enable (mre) to "1". as a result, the first monitor byte is acknowledged by the receiving device setting the mr bit to "0". this causes a monitor data acknowledge (mda) interrupt status at the transmitter. a new monitor data byte can now be written by the microprocessor in mox. the mx bit is still in the active ("0") state. the transmitter indicates a new byte in the monitor channel by returning the mx bit active after sending it once in the inactive state. as a result, the receiver stores the monitor byte in mor and generates a new mdr interrupt status. when the microprocessor has read the mor register, the receiver acknowledges the data by returning the mr bit active after sending it once in the inactive state. this in turn causes the transmitter to generate an mda interrupt status. this "mda interrupt C write data C mdr interrupt C read data C mda interrupt" handshake is repeated as long as the transmitter has data to send. note that the monitor channel protocol imposes no maximum reaction times to the microprocessor. when the last byte has been acknowledged by the receiver (mda interrupt status), the microprocessor sets the monitor transmit control bit (mxc) to "0". this enforces an inactive ("1") state in the mx bit. two frames of mx inactive signifies the end of a message. thus, a monitor channel end of reception (mer) interrupt status is generated by the receiver when the mx bit is received in the inactive state in two consecutive frames. as a result, the microprocessor sets the mr control bit mrc to "0", which in turn enforces an inactive state in the mr bit. this marks the end of the transmission, making the monitor channel active (mac) bit return to "0". during a transmission process, it is possible for the receiver to ask for a transmission to be aborted by sending an inactive mr bit value in two consecutive frames. this is effected by the microprocessor writing the mr control bit mrc to "0". an aborted transmission is indicated by a monitor channel data abort (mab) interrupt status at the transmitter. in te mode, the adf2:te1 bit is used to direct the monitor access either to iom ? -2-channel 0 (adf2:te1 = "0", default) or to iom ? -2-channel 1 of the iom ? -2-terminal structure. this allows to program terminal devices such as the arcofi ? via the processor interface of the iec-q. if the adf2:te1 bit is "1", the monitor channel on iom ? -2-channel 0 is passed transparently from the iom ? -2 interface to the transceiver core. peb 2091 pef 2091 operational description semiconductor group 106 data sheet 01.99 4.2 access to u-interface the u-frame is not directly accessible by the user. communication with the u-interface will be established using the user interfaces iom ? -2, p (if used) or pins. this chapter shows how this can be done for both receive and transmit directions. figures 44 and 45 sketch the available ways of access to the different channels of the u-interface data in both directions. for more details about the structure of the u-frame, see "u -frame structure", page 67. for blocks functions, see "system interface unit", page 62. in addition, section 4.2.4, page 124, describes how the u-interface superframe marker can be set and indicated. figure 44 channels of access to u-interface (transmitter) u basic frame 1.5 ms (i)sw fixed 18 bits data 12x (2b+d) 216 bits m1-m3 3 bits m4 1 bit m5-m6 2 bit time transmitter data (to u) transmiter fifo 2b+d 1) eoc processor mon-0 1) single bits processor crc processor (2b+d & m4) 3) mon-1 1)2) mon-2 1) ps1,ps2 2) 1) from iom ? -2 or p 2) applies only in nt modes 3) from the last u superframe. not directly accessable to user peb 2091 pef 2091 operational description semiconductor group 107 data sheet 01.99 data during normal operation (i.e. transparent transmission and no test mode) the 2b+d channels can be accessed via the iom ? -2 or the p interface, if used. see section 4.2.1, page 108 for details. eoc basically the eoc channel can be accessed via mon-0 messages. however, internal processing, manipulation and filtering of the eoc messages could take place automatically, depending on the mode chosen. for details see section 4.2.2, page 110. figure 45 channels of access to u-interface (receiver) time receiver data (from u) 1) to iom ? -2 and p (if used) 2) crc bits not accessable to user u basic frame 1.5 ms (i)sw fixed 18 bits data 12x (2b+d) 216 bits m1-m3 3 bits m4 1 bit m5-m6 2 bit receiver fifo 2b+d 1) eoc processor mon-0 1) single bits processor mon-1 1) mon-2 1) crc 2) processor peb 2091 pef 2091 operational description semiconductor group 108 data sheet 01.99 single bits user access to the single bits (sb) channel is mode dependent. in transmit direction there are five possible sources for setting (different) sb: mon-1 messages, mon-2 messages, mon-8 messages, the pins ps1 and ps2 and the state machine. mon-1, mon-2 and pins ps1 and ps2 can be manipulated directly by the user. bits controlled by the state machine can not be manipulated by the user in a direct way. in the receive direction the sb are given via mon-1 and mon-2 messages. several filtering methods are available. for details see section 4.2.3, page 115. note 31: u-interface data is scrambled before it is send to the u-interface and descrambled when they are received from the u-interface (see "scrambler / descrambler", page 62). note 32: the synchronization words (bits 1-18 of each u basic frame) are set by the transceiver core and can not be manipulated by the user. note 33: the crc channel can not be accessed by the user. these bits are calculated and set by the transceiver core automatically (see "cyclic redundancy check (crc)", page 64). however there are several methods of monitoring crc violations, which are discussed in detail in chapter 4.5, page 176. 4.2.1 access to data channels of u-interface figures 46 and 47 below sketch how data can generally be accessed by the user. figure 46 access to data transmission on u u basic frame 1.5 ms (i)sw fixed 18 bits data 12x (2b+d) 216 bits m1-m3 3 bits m4 1 bit m5-m6 2 bit time transmitter data (to u) transmiter fifo 2b+d from iom ? -2 or p peb 2091 pef 2091 operational description semiconductor group 109 data sheet 01.99 data access in lt mode in lt modes (see "setting operating modes", page 50) transparent data access is available in both directions in the states: i.e. when the iec-q issues the signal sl3t on u, and the receiver is synchronized (see "state transition diagram in lt modes", page 147). in these states data from upstream is handed over via transmit fifo to the u-frame in the same order it is received. data from downstream is handed over via receive fifo to the iom ? -2 interface and to the microprocessor interface (if used) in the same order it is received. data access in nt mode in nt modes (see "setting operating modes", page 50) transparent data access will be available in both directions in the states "transparent", "error s/t" and "pending deactivation u", i.e. when the iec-q issues the signal sn3t on u (see "state transition diagram in nt, te and nt-pbx modes", page 161). if test loop #2 is not closed in the iec-q (see "test loop-backs", page 186) data from downstream is handed over via transmit fifo to the u-frame in the same order it is received. data from upstream is handed over via receive fifo to the iom ? -2 interface and to the microprocessor interface (if used) in the same order it is received. lt lt-rp pending transparent pending transparent transparent transparent pending deactivation pending deactivation line active s/t deactivated peb 2091 pef 2091 operational description semiconductor group 110 data sheet 01.99 figure 47 access to data received from u 4.2.2 access to eoc of u-interface the mon-0-commands provide access to device internal eoc-registers. via mon-0 the eoc overhead bits of the u-interface are controlled. this access is only possible in states where the iec-q transmits superframe indications (isw) and the receiver is synchronized. this is the case in the following states: figures 48 and 49 sketch eoc access in these states. lt modes nt modes ec-converged synchronized eq-training wait for act line active transparent pend. transparent error s/t transparent pend. deac. u pend. deactivation s/t deactivated time receiver data (from u) u basic frame 1.5 ms (i)sw fixed 18 bits data 12x (2b+d) 216 bits m1-m3 3 bits m4 1 bit m5-m6 2 bit receiver fifo 2b+d to iom ? -2 and p (if used) peb 2091 pef 2091 operational description semiconductor group 111 data sheet 01.99 figure 48 access to eoc transmission on u figure 49 access to eoc received from u in other states the eoc-processor clamps all eoc-maintenance bits to high when eoc-bits are transmitted. the address bits, d/m bit and the eoc code of the two byte mon-0 message (see table 18 below) corresponds to the address bits , d/m bits and eoc code in the eoc channel of the u-interface (see "u-frame structure", page 68). for more information on monitor channel handling, see "iom ? -2 monitor channel", page 76 and for the microprocessor mode "monitor channel access", page 101. for a complete list of the available monitor channel commands, see "mon-0 codes", page 226. table 18 content of mon-0 message 1. byte 2. byte 0 0 0 0 a a a | 1 e e e e e e e e mon-0 addr. | d/m eoc code u basic frame 1.5 ms (i)sw fixed 18 bits data 12x (2b+d) 216 bits m1-m3 3 bits m4 1 bit m5-m6 2 bit time transmitter data (to u) eoc processor mon-0 from iom ? -2 or p time receiver data (from u) u basic frame 1.5 ms (i)sw fixed 18 bits data 12x (2b+d) 216 bits m1-m3 3 bits m4 1 bit m5-m6 2 bit eoc processor mon-0 to iom ? -2 and p (if used) peb 2091 pef 2091 operational description semiconductor group 112 data sheet 01.99 mon-0-commands may be passed at any instant and need to be transferred only once (applicable for auto and transparent mode). code repetition is performed within the chip by the eoc processor. a summery of the eoc procedure in eoc auto and transparent modes is given in figure 50, page 114. if the microprocessor mode is used, the iom ? -2 interface in figure 50 can be replaced by the p interface. eoc access in lt- auto mode in lt-auto mode the "return message" reception is enabled after an eoc-command has been transmitted downstream. the activation of this function causes the lt iec-q to watch the eoc of the u-interface and to issue a mon-0-message after an identical eoc-message has been received during three consecutive frames. thus in lt-auto mode an acknowledgment of the mon-0-command is even possible if the new message is not different from the previous one. if no mon-0-command has been transmitted downstream, a mon-0-message is issued only after the "triple-last-look" criterion is fulfilled and if this message is different from the one previously accepted. new messages will be passed upstream independently of the address used, i.e. not only messages addressed with (000) or (111) but all received eoc-messages will be transmitted with mon-0-messages. lt-transparent mode in lt-transparent mode every 6 ms a mon-0-message containing the last received eoc-message is issued. this occurs even if no change occurred in the eoc-channel. no "triple-last-look" is performed before a mon-0-message is sent. nt-eoc-auto mode the seven defined eoc-commands listed in table 19 will be executed automatically by the iec-q if they were sent with the address (000) or (111) and the d/m bit was set to message (1). every new eoc-command will be acknowledged immediately, i.e. no triple-last-look (e.g. acknowledgment of lb1 command reads 01 h , 51 h ) before the acknowledgment is transmitted. table 19 predefined eoc messages code hex. symbol function 00 h hold 50 lbbd close complete loop 51 lb1 close loop b1 52 lb2 close loop b2 peb 2091 pef 2091 operational description semiconductor group 113 data sheet 01.99 if a command is declared as data (d/m = (0)), the iec-q will acknowledge with "utc" (i.e. 01aa h ). commands addressed different from (000 b ) or (111 b ) will be acknowledged with the "hold" message and the correct nt address (i.e. 0100 h ), see "predefined eoc codes", page 231, for a complete list. all detected eoc-commands on u are latched, i.e. they are valid as long as they are not explicitly disabled with the eoc "rtn" command or a deactivation. each new eoc-command will be indicated with one single mon-0-message after the triple-last-look criterion has been met (also if other addresses than (000) or (111) or d/m = (0) are used). the verified message is not compared to the last accepted message (triple-last-look). instead a mon-0-message will be issued every time the new verified message is different from the last. e.g. in case bit errors corrupted an eoc-command the correct command will be reissued after error free transmission is resumed. the execution of a correctly addressed command (000 b or 111 b ) is performed only after the "triple-last-look" criterion is met. mon-0-commands given via iom ? -2 (din) or microprocessor interface will be ignored. nt-transparent mode every 6 ms a mon-0-message is issued on iom ? -2. it contains the last received eoc-message. no acknowledgment, no triple-last-look, no execution of the received commands is performed in eoc transparent mode. all these actions have to be initiated by a control unit. with mon-8-messages all defined test functions (close/open loops, send corrupted crcs) can be executed in the nt, see "test loop-backs", page 186. 53 rcc request corrupt crc 54 ncc notify of corrupt crc aa utc unable to comply ff rtn return to normal xx acknowledge table 19 predefined eoc messages peb 2091 pef 2091 operational description semiconductor group 114 data sheet 01.99 figure 50 eoc-procedure in auto and transparent mode itd04233 mon-0 eoc nt u eoc m1, m2, m3, lt eoc mon-0 a echo execute t x 3 3x t a t a transmit request will enable return message transmission possible arm (c/i) indication uai (c/i) indication reception possible eoc mon-0 mon-0 eoc 3, m 2, m 1, m eoc a: t: auto-mode transparent-mode r iom -2 r iom -2 r iom -2 r iom -2 7 peb 2091 pef 2091 operational description semiconductor group 115 data sheet 01.99 4.2.3 access to the single bits of u-interface the transmission procedure of the single bits (sb) on the u-interface is mode dependent. the reception procedure of the sb from the u-interface is independent 1) of the mode used. transmission and reception of sb will therefore be discussed in to different sections below. for definition of single bits, see "single bits channel", page 69. for more information on monitor channel handling, see "iom ? -2 monitor channel", page 76, and for the microprocessor mode "monitor channel access", page 101. correspondence between mon-2 messages and sb the content of the mon-2 message (table 20) corresponds to the single bits in the u-frame (see "u-frame structure", page 68). bit m46 in the mon-2 message, for example, will be inserted at position m46 in the u-frame. 4.2.3.1 single bits transmission on u figure 51 sketches roughly how transmitted single bits can be accessed. figure 51 access to single bits transmission on u the single bits defined by a mon-2 message are latched. i.e. they need to be issued only once. repetition will be performed by the sb processor. if no mon-2 messages are 1) exception: the default setting of the repeater modes for sb indication is different than the default setting in other modes, see "single bits reception from u", page 120 table 20 content of mon-2 message 1. byte 2. byte 0 0 1 0 m41 m51 m61 m42 m52 m62 m43 m44 m45 m46 m47 m48 mon-2 overhead bits overhead bits u basic frame 1.5 ms (i)sw fixed 18 bits data 12x (2b+d) 216 bits m1-m3 3 bits m4 1 bit m5-m6 2 bits time transmitter data (to u) sb processor mon-1 1) , mon-2, mon-8 from iom ? -2 or p pins ps1 and ps2 1) 1) applies only in nt modes peb 2091 pef 2091 operational description semiconductor group 116 data sheet 01.99 issued, the corresponding position in the sb channel will be set to "1", which is the default value after the signal sl2 in the lt modes and sn3 in the nt modes are issued on the u-interface (see state machines, pages 146, 160 and 173). sb transmission in nt modes note 34: this section applies if one of the modes nt, nt-auto activation, te and nt-pbx is used (see "basic operating mode", page 50). the single bits will be set in the following manner: ? the single bit act is controlled internally by the activation/deactivation state machine (see "state machine in nt modes", page 160) ? two different ways are available to control the single bit sai: 1- internally by the activation/deactivation state machine (see "state machine in nt modes", page 160), which is the default setting after power up. 2- by the mon-2 command. control via mon-2 can be set by issuing the mon-8 command pace. to change this setting back to iec-q internal control (1), the mon-8 command paca can be issued. (see "mon-8 codes", page 228, for details about codes and programming of these commands). ? the single bit febe is controlled internally by the crc processor (see "monitoring transmission quality", page 176). in addition the mon-8 message sfb can be issued to set the febe bit to "0" once in the next available superframe (test mode, see "mon-8 codes", page 228, for details mon-8 codes and programming). ? the single bit cso is set to "0". ? the single bits ps1 and ps2 are programmed directly by the pins ps1 and ps2 respectively (see "power controller pins", page 36 and page 45). any change in the pin polarity will be indicated at the corresponding position and transmitted in the next available superframe (see "monitoring primary and secondary nt power supply", page 194). ? the bit ntm is programmed via the m-bits of the mon-1 messages ntm and norm (see "mon-8 codes", page 228). ? all of other single bits, i.e. m46, m48 m51, m52 and m61 can be set by the user via mon-2 messages. table 21 gives an overview of sb control, and table 22 gives a brief explanation of the function of the sb in this mode. table 21 single bits control in nt modes (upstream) position nt C> lt mon-2/u bit control m41 act state machine (iec-q) m51 1 mon-2 peb 2091 pef 2091 operational description semiconductor group 117 data sheet 01.99 m61 1 mon-2 m42 ps1 pin ps1 m52 1 mon-2 m62 febe crc processor (iec-q) and mon-8 m43 ps2 pin ps2 m44 ntm mon-1 m45 cso "0" (iec-q) m46 1 mon-2 m47 sai state machine (iec-q) / mon-2 m48 1 mon-2 table 22 function of the predefined sb in nt modes bit function act (activation bit) the act-bit is part of the start-up sequence and is used to indicate layer 2 to be ready for communication. in this case it is set to (1) cso (cold start only) the cso-bit signals the network side whether the nt is only capable of being started via cold start sai (s activity indicator) the sai-bit informs the lt side about the state of the s-interface. with the s-interface deactivated (i.e. c/i-commands tim or di received), the sai-bit is set to (0). additionally the bit sai is used (with sai = (1)) in a terminal initiated activation (if the u-interface was active before) to request complete nt activation febe (far-end block error) the febe-bit is used to inform the opposite u-interface station that the transmitted data could not be received free of errors. the device sets the febe-bit to (0) if errors were observed. each time a febe = (0) is detected, the count of the internal far-end block error counter will be incremented. additionally it is possible to control the febe-bit with the mon-8-message "sfb" table 21 single bits control in nt modes (upstream) peb 2091 pef 2091 operational description semiconductor group 118 data sheet 01.99 sb transmission in lt modes note 35: this section applies in lt and cot modes (see "basic operating mode", page 50). the single bits will be set in the following manner: ? the single bits act and dea are controlled internally by the activation/deactivation state machine (see "state machine in lt modes", page 146). ? two different ways are available to control the single bit uoa: 1- internally by the activation/deactivation state machine (see "state machine in lt modes", page 146), which is the default setting after power up. 2- by the mon-2 command. control via mon-2 can be set by issuing the mon-8 command pace. to change this setting back to iec-q internal control (1), the mon-8 command paca can be issued. (see "mon-8 codes", page 228, for details about codes and programming of these commands). ? the single bit febe is controlled internally by the crc processor (see "monitoring transmission quality", page 176). in addition the mon-8 message sfb can be issued to set the febe bit to "0" (test mode, see "mon-8 codes", page 228, for details mon-8 codes and programming). ? all other single bits, i.e. m43-m46, m48 m51, m52 and m61 can be set by the user via mon-2 messages. table 21 gives an overview of sb control, and table 22 gives a brief explanation of the function of the sb in this mode. ps1 (power status primary source) the ps1-bit is used to indicate the status of the primary nt power supply. it is set to (1) if the level at pin ps1 is high. ps1 = (1) indicates that the primary power supply is normal ps2 (power status secondary source) the ps2 bit is used to indicate the status of the secondary nt power supply. it is set to (1) if the level at pin ps2 is high. ps2 = (1) indicates that the secondary power supply is normal ntm (nt test mode) this bit informs the network side that the nt is involved in terminal initiated tests and therefore is not available for transparent transmission. the ntm-bit set to (0) indicates that the nt is in a test mode. the ntm-bit is set to (0) with the mon-1 command "ntm" and is reset to (1) by "norm" table 22 function of the predefined sb in nt modes bit function peb 2091 pef 2091 operational description semiconductor group 119 data sheet 01.99 table 23 single bits control in lt modes (downstream) position lt C> nt mon-2/u bit control m41 act state machine (iec-q) m51 1 mon-2 m61 1 mon-2 m42 dea state machine (iec-q) m52 1 mon-2 m62 febe crc processor (iec-q) and mon8 m43 1 pin ps2 m44 1 mon-1 m45 1 "0" (iec-q) m46 1 mon-2 m47 uoa state machine (iec-q) / mon-2 m48 1 mon-2 table 24 function of the predefined sb in lt modes bit function act (activation bit) the act-bit is part of the start-up sequence and is used to indicate layer 2 to be ready for communication. in this case it is set to (1) dea (deactivation bit) by setting dea to (0), the network informs the nt of its intention to turn-off uoa (partial activation) the uoa-bit is used by the network side to inform the nt that only the u-interface shall be activated (s-interface remains deactivated. if the uoa-bit is set to (0), only the u-interface will be activated febe (far-end block error) the febe-bit is used to inform the opposite u-interface station that the transmitted data could not be received free of errors. the device sets the febe-bit to (0) if errors were observed. each time a febe = (0) is detected, the internal far-end block error counter will be incremented. additionally it is possible to control the febe-bit with the mon-8-message "sfb" peb 2091 pef 2091 operational description semiconductor group 120 data sheet 01.99 sb transmission in repeater modes note 36: this section applies to nt-rp and nt-rp modes (see "basic operating mode", page 50). in these modes all of the single bits need to be controlled via mon-2-messages. this permits to implement national repeater specifications for overhead bit treatment. for a short explanation of the function of the sb in both nt and lt modes refer to tables 22 and 24 above. 4.2.3.2 single bits reception from u the received single bits from the u-interface are forwarded via mon-2 messages to the controller unit 1) to allow higher layer evaluation of these data. figure 52 access to single bits received from u the iec-q version 5.3 allows almost free control of the conditions for single bits verification. single bits can be filtered and forwarded in one of the following ways: ? a mon-2 is issued if the polarity of at least one of the single bits, other than febe, has been changed. (compatible to version 5.1). ? a mon-2 message will be issued only if in addition no crc violations have been detected in the completed last two superframes. (compatible to all previous iec-q versions other than version 5.1). ? furthermore, verification of single bits changes can be chosen to be controlled by a triple last look processor. choosing this filtering method will imply that a change in a single bit will be issued via mon-2 message only if an identical bit value has been received for three consecutive superframes. 1) upstream in the lt modes and downstream in the nt modes time receiver data (from u) u basic frame 1.5 ms (i)sw fixed 18 bits data 12x (2b+d) 216 bits m1-m3 3 bits m4 1 bit m5-m6 2 bit sb processor mon-1, -2 to iom ? -2 and p (if used) peb 2091 pef 2091 operational description semiconductor group 121 data sheet 01.99 the last setting for the m4 bits complies with ansi t1.601 without need for further software efforts. note that this is the default setting for the m4 bits in all non repeater modes (see table 26). note also that this filtering method setting can be combined with the crc filtering method. in addition, the verification of the m4 bits is completely independent of the verification of bits m51, m52 and m61. this allows using the m4 bits in compliance with ansi t1.601 (triple last look), and still retain the freedom to use bits m51, m52 an m61 for other purposes (i.e. control functions, or even very low rate data transmission). control of the single bits is mode independent. this allows more flexibility, e.g. in repeater applications. selection of the filtering method is controlled via mon-8 messages. it is therefore available in stand-alone mode as well as in p mode. definitions as selection of the verification method for single bits is done via mon-8 messages, it is convenient to recall the format of mon-8 messages, which is given in table 25 below. for more details on mon-8 messages, see "mon-8 codes", page 228. r: register address C 0 = local function register C 1 = internal register d07 local command C 00 ff h = local function code C 00 ff h = internal register address the mon-8 commands used to control the verification method are all local functions. the register bit "r" should therefore be always set to "0". for definition of the single bits, see "single bits channel", page 69. in what follows we will refer to bits m41 to m48 as "m4 bits" . bits m51, m52 and m61 will be referred to as "additional overhead bits". table 25 format of mon-8-messages 1. byte 2. byte 1 0 0 0 r | 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 mon-8 register | addr. local command (message/data) peb 2091 pef 2091 operational description semiconductor group 122 data sheet 01.99 verification control for m4 bits table 26 gives the available settings for m4 bits filtering via mon-8 command. table 26 setting filtering method for m4 bits code d7-d0 (bin) 1) 1) see table 25 for definition symbol function 1000 1110 tll (default, not rp) a change in at least one of the m4 bits will be passed via mon-2 only after valid triple last look. this is the default setting after reset in all non repeater modes 1000 1101 crc (default, rp) a change in at least one of the m4 bits will be passed via mon-2 only if the crc is valid for the last two superframes, not including the current one. this is the default setting after reset in the repeater modes 1000 1111 tll, crc a change in at least one of the m4 bits will be passed via mon-2 only after valid triple last look, and if the crc is valid for the last two superframes, not including the current one 1000 1100 on change every change in at least one of the m4 bits will be passed via mon-2 peb 2091 pef 2091 operational description semiconductor group 123 data sheet 01.99 verification control for additional overhead bits table 27 gives the available settings for additional overhead bits (m51, m52, m61) filtering via mon-8 command. reset behavior mon-2 messages will be issued only if the receiver is synchronized. this is done to avoid meaningless mon-2 messages if data transmission is not synchronized. in other words, mon-2 messages will be issued only in the following states: in the lt mode ( page 147) : "line active", "pend. transparent", "s/t deactivated", "pend. deactivation" and "transparent". in the nt mode (page 161) : "synchronized 1", "synchronized 2", "wait for act", "transparent", "error s/t", "pend. deact. s/t", "pend. deact. u" and "analog loop back". in the lt-repeater mode ( page 174) : "pend. transparent", "transparent", "pend. deactivation". in the nt-repeater mode ( page 175) : "synchronized", "transparent", "error", "pend. deact." and "analog loop back". mode setting via mon-8 will be reset only if the "test" state is entered (see "state machine in lt modes", page 146), i.e. after uvd, hardware reset, software reset or power-on reset. table 27 setting filtering method for additional overhead bits code d7-d0 (bin) 1) 1) see table 25 for definition symbol function 1000 1010 tll (default, not rp) a change in at least one of the additional overhead bits will be passed via mon-2 only after valid triple last look. this is the default setting after reset in all non repeater modes 1000 1001 crc (default, rp) a change in at least one of the additional overhead bits will be passed via mon-2 only if the crc is valid for the last two superframes, not including the current one. this is the default setting after reset in the repeater modes 1000 1011 tll, crc a change in at least one of the additional overhead bits will be passed via mon-2 only after valid triple last look, and if the crc is valid for the last two superframes, not including the current one 1000 1000 on change every change in at least one of the additional overhead bits will be passed via mon-2 peb 2091 pef 2091 operational description semiconductor group 124 data sheet 01.99 4.2.4 setting superframe marker in the nt and te modes, with superframe marker selected (see "setting modes of operation (stand-alone and p mode)", page 51) the start of a new superframe is indicated with a fsc high-phase lasting for one single dcl-period. a fsc high-phase of two dcl-periods is transmitted for all other iom ? -2-frame starts. in lt modes the superframe marker can be indicated by a short frame synchronization signal (fsc) of the iom ? -2 interface. if the high phase of fsc lasts one dcl period or less, the u-interface frame will be reset and the inverted synchronization word (isw) will be inserted at the beginning of the next available basic frame. the remaining 95 fsc-clocks must be of at least two dcl-periods duration. if no superframe marker is to be used, all fsc high-phases need to be of at least two dcl-periods duration. the relationship between the iom ? -2-superframe marker of the slave, the u-interface, and the iom ? -2 superframe marker of the master is fixed after activation of the u-interface. i.e. data inserted on lt side in the first b1-channel after the iom ? -2-slave superframe marker will always appear on the nt side with a fixed offset, e.g. in the 5th b1-channel after the master superframe marker. after a new activation this relationship (offset) may be different. superframe marker enable in p mode note 37: this feature is only available in the p-lt modes. as mentioned above, in lt modes the superframe marker can be indicated by a short frame synchronization signal (fsc) of the iom ? -2 interface. consequently, spikes on the fsc might be unintentionally recognized as superframe marker by the iec-q. in most cases (> 85%) such a spike will introduce permanent high bit error rate. it is therefore very important to make sure, that no spikes on pin fsc could occur. however, cases were reported where spikes on pin fsc couldnt be avoided. version 5.3 of the iec-q offers a way to overcome this problem. setting bit sfen of register adf2 (see "adf2-register", page 214) to "0" will disable the superframe marker function. this prevents spikes on fsc to trigger superframes. bit errors caused by the additional fsc pulses will not last longer than 3 iom ? -2 frames. note 38: setting adf2:sfen to "0" will introduce the same behavior as version 5.2 (refer to the corresponding point in delta sheet of the peb/f 2091 v5.2). however, the value of adf2:sfen after reset will be "1", which means that the superframe marker function is enabled by default and therefore compatible to all iec-q versions up to 5.1. peb 2091 pef 2091 operational description semiconductor group 125 data sheet 01.99 4.3 layer 1 activation and deactivation the iec-q is designed to meet the newest standards of ansi and etsi regarding status control. the following sections describe some of the most important protocols implemented in the iec-q. they illustrate the interaction between the stations involved. all information presented in this section is extracted from the state machines (see "state machines", page 145). table 28 shows all u-interface signals as defined by ansi. table 28 u-interface signals signal synch. word (sw) superframe (isw) 2b + d m-bits nt C> lt tn 1) 1) alternating 3 symbols at 10 khz 3 3 3 3 sn0 no signal no signal no signal no signal sn1 present absent 1 1 sn2 present absent 1 1 sn3 present present 1 normal sn3t present present normal normal lt C> nt tl 1) 3 3 3 3 sl0 no signal no signal no signal no signal sl1 present absent 1 1 sl2 present present 0 normal sl3 2) 2) must be generated by the exchange present present 0 normal sl3t present present normal normal test mode sp 3) 3) alternating 3 single pulses of 12.5 m s duration spaced by 1.5 ms, else no signal 3 peb 2091 pef 2091 operational description semiconductor group 126 data sheet 01.99 4.3.1 complete activation initiated by lt figure 53 depicts the procedure if the activation has been initiated by the exchange side. if activation is initiated with the c/i code ar, as shown in figure 53, activation will fail if the signal sn3 hasnt been correctly received within 15 seconds. in this case the lt side will indicate the c/i code ei3 instead of uai and the device should be reset (see "lt modes state diagram", page 147). in normal lt-nt configurations these 15 seconds are much longer than average activation time which lies between 1-7 seconds, depending on line characteristics, i.e. if this timer expires it is a strong indication for an error condition. in some configurations, however, e.g. a line with several repeaters, this timer could expire under normal activation condition. for such configurations the iec-q provides the c/i command arx which can be used instead of the command ar for activation. if activated with the arx command the iec-q will continue the activation procedure, even if the 15 seconds timer has expired. figure 53 complete activation initiated by lt itd04241 dc di dc di sl3t pu u-reference point sbcx iec-q iec-q nt lt s/t arm act = 0 dea = 1 uoa = 1 0 info 0 info ar ar sl0 sn0 tl tn sn1 sn0 sl1 1 = uoa 1 = dea 0 = act sl2 sn2 0) (sai 0 = act sn3 = ai dc = sn3 act = 0 sai 1 sn3t sl3t ar ar ai ai info 3 info 2 4 info uai 1 sai 1 = act sn3 = 1 = uoa 1 = dea 1 = act sl3t r epic r iom -2 r iom -2 peb 2091 pef 2091 operational description semiconductor group 127 data sheet 01.99 4.3.2 activation with act-bit status ignored by the exchange side activation with c/i-command "ar0" forces the state machine into the state "line active" independently of the act-bit status transmitted upstream from the network. activation may be completed after the act-bit evaluation has been enabled with c/i-command "ar". figure 54 activation with act-bit status ignored by the exchange itd04242 dc di dc di sl3t pu ar u-reference point sbcx iec-q iec-q nt lt s/t arm act = 1 dea = 1 uoa = 1 0 info 0 info ar ar0 sl0 sl0 tl tn sn1 sn0 sl1 0 = uoa 1 = dea 0 = act sl2 sn2 0) (sai 0 = act sn3 = ai dc 0 = uoa 1 = dea 0 = act sl3t 1 = uoa 1 = dea 0 = act sl3t = sn3 act = 0 sai 1 1 sai 1 = act sn3 = sn3t sl3t ar ar ai ai info 3 info 2 4 info uai uoa = 1 mon2 r epic r iom -2 r iom -2 : peb 2091 pef 2091 operational description semiconductor group 128 data sheet 01.99 4.3.3 complete activation initiated by te figure 55 depicts the procedure if the activation has been initiated by the terminal side. figure 55 complete activation initiated by te itd04243 dc di dc di sl3t uoa = 1 uai u-reference point s/t arm info 0 info 0 ar sl0 sn0 tn sn1 sn0 sl1 sl2 act = 0 dea = 1 uoa = 0 sn2 sn3 sai = 1 dc info 1 tim pu ar ar r iom -2 r iom -2 sn3 act = 1 sai = 1 sl3t act = 1 dea = 1 uoa = 1 sn3t ai ai info 3 info 0 info 2 info 4 sbcx iec-q te iec-q epic nt lt r ai peb 2091 pef 2091 operational description semiconductor group 129 data sheet 01.99 4.3.4 complete deactivation figure 56 complete deactivation itd04244 ai ai ar ai sl3t sn3t dr di dc info 0 info 0 u-reference point sbcx iec-q iec-q nt lt s/t dr di act = 1 dea = 1 uoa = 1 act = 1 sai = 1 0 = dea 0 = act sl3t 4 info 3 info dc deac 3ms ms 40 40 ms 3ms sl0 sn0 r iom -2 r iom -2 r epic peb 2091 pef 2091 operational description semiconductor group 130 data sheet 01.99 4.3.5 partial activation (u only) the iec-q is in the "synchronized 1" state (see "state machine in nt modes", page 160) after a successful partial activation. iom ? -2-clocks dcl and fsc are issued. on dout the c/i-message "dc" as well as the lt user data is sent. while the c/i-messages "di" (1111 b ) or "tim" (0000 b ) are received on din, the iec-q will transmit "sai" = (0) upstream. any other code results in "sai" = (1) to be sent. on the u-interface the signal sn3 (i.e. 2b + d = (1)) will be transmitted continuously regardless of the data on received from the downstream side. the lt will transmit all user data transparently downstream (signal sl3t). in case the last c/i command applied is "uar", the lt retains activation control when an activation request comes from the terminal (confirmation with c/i = "ar" required, see page 132 (case 1)). with c/i "dc" applied from the upstream device, te initiated activations will be completed without the necessity of an exchange confirmation (page 133 (case 2)). figure 57 u only activation itd04245 dc di dc di sl3t pu uai u-reference point sbcx iec-q iec-q nt lt s/t arm act = 0 dea = 1 uoa = 1 0 info 0 info ar uar sl0 sn0 tl tn sn1 sn0 sl1 0 = uoa 1 = dea 0 = act sl2 sn2 0 sai 0 = act sn3 = (dc) dc r epic r iom -2 r iom -2 peb 2091 pef 2091 operational description semiconductor group 131 data sheet 01.99 4.3.6 activation initiated by lt with u active the s-interface is activated from the exchange with the command "ar". bit "uoa" changes to (1) requesting s-interface activation. figure 58 lt initiated activation with u-interface active itd04246 dc di dc/uar uai sl3t sn3 ar ai ai info 3 info 2 ai u-reference point sbcx iec-q iec-q nt lt s/t uai act = 0 dea = 1 uoa = 0 act = 0 sai = 0 1 = uoa 1 = dea 0 = act sl3t 1 = sai 1 = act sn3 sl3t act = 1 dea = 1 uoa = 1 0 info 0 info info 4 ar sn3t sl3t ar ar sn3 act = 0 sai = 1 r epic r iom -2 r iom -2 peb 2091 pef 2091 operational description semiconductor group 132 data sheet 01.99 4.3.7 activation initiated by te with u active the te initiates complete activation with info 1 leading to "sai" = (1). case 1 requires the exchange side to acknowledge the te activation by sending c/i = "ar", case 2 activates completely without any lt confirmation. figure 59 te activation with u active and exchange control (case 1) itd04247 dc di uar uai sl3t sn3 ar ai ai info 3 info 2 ai u-reference point sbcx iec-q iec-q nt lt s/t uai act = 0 dea = 1 uoa = 0 act = 0 sai = 0 1 = uoa 1 = dea 0 = act sl3t 1 = sai 1 = act sn3 sl3t act = 1 dea = 1 uoa = 1 0 info 0 info info 4 info 1 ar 1 = sai 0 = act sn3 sn3t sl3t ar ar r epic r iom -2 r iom -2 peb 2091 pef 2091 operational description semiconductor group 133 data sheet 01.99 figure 60 te activation with u active and no exchange control (case 2) itd04248 dc di dc uai sl3t sn3 ar ai ai info 3 info 2 ai u-reference point sbcx iec-q iec-q nt lt s/t uai act = 0 dea =1 uoa = 0 act = 0 sai = 0 1 = uoa 1 = dea 0 = act sl3t 1 = sai 1 = act sn3 sl3t act = 1 dea =1 uoa =1 0 info 0 info info 4 info 1 ar 1 = sai 0 = act sn3 sn3t sl3t ar r epic r iom -2 r iom -2 peb 2091 pef 2091 operational description semiconductor group 134 data sheet 01.99 4.3.8 deactivating s/t-interface only deactivation of the s-interface without deactivating the u-interface is initiated from the exchange by setting the "uoa" bit = (0). figure 61 deactivation of s/t only itd04249 ai ai ar ai sl3t sn3t dr di dc info 0 info 0 (dc) u-reference point sbcx iec-q iec-q nt lt s/t uar uai act = 1 dea = 1 uoa = 1 act = 1 sai = 1 0 = uoa 1 = dea 1 = act sl3t 0 = sai 0 = act sn3 sl3t act = 0 dea = 1 uoa= 0 4 info 3 info r iom -2 r iom -2 r epic peb 2091 pef 2091 operational description semiconductor group 135 data sheet 01.99 4.3.9 activation initiated by lt with repeater figure 62 activation with repeater initiated by lt itd04250 di dc pu tim dc di di dc ar info 0 info 0 u-ref. point sbcx iec-q iec-q iec-q iec-q nt repeater lt s/t lt-rp nt-rp tn tn ar ar arm ar info 2 uai ai ai ai uai arm tl tl dc ar sn0 sl0 sn1 sn0 sl1 sl2 sn2 sn3t sl3t sn0 sl0 sn1 sn0 sl1 sl2 sn2 sn3t sl3t pu dc r epic r iom -2 r iom -2 r iom -2 r iom -2 point u-ref. peb 2091 pef 2091 operational description semiconductor group 136 data sheet 01.99 4.3.10 activation initiated by te with repeater figure 63 activation with repeater initiated by te itd04251 dc di tim pu di dc dc di ar info 0 info 0 tim pu u-ref. point sbcx iec-q iec-q iec-q iec-q nt repeater lt s/t lt-rp nt-rp info 1 ar dc tn ar ar tn ar ar arm ar info 2 uai ai ai ai uai (free running) arm sl0 sn0 sn1 sn0 sl1 sl2 sn2 sn3 sl3t sl0 sn0 sn1 sn0 sl1 sl2 sn2 sn3t sl3t r epic r iom -2 r iom -2 r iom -2 r iom -2 u-ref. point peb 2091 pef 2091 operational description semiconductor group 137 data sheet 01.99 4.3.11 loss of synchronization / signal at repeater figure 64 loss of synchronization at repeater (lt side) itd04252 ai ai ai ai ai ar ar ai dr di dc 40 ms info 0 info 0 dc 40 ms di tim dc pu 3ms u-ref. point u-ref. point sbcx iec-q iec-q iec-q iec-q nt repeater lt s/t 3ms dr deac dc di dea = 0 lsl 480 ms lt-rp nt-rp dea = 0 loss of sync. 480 ms res1 ei 1 dr sl3t sn3t sl0 sn0 sl3t sn3t sl3t sl0 sn0 r epic r iom -2 r iom -2 r iom -2 r iom -2 peb 2091 pef 2091 operational description semiconductor group 138 data sheet 01.99 figure 65 loss of signal at repeater (lt side) itd04253 ai ai ai ai ai ar ar ai sl3t sn3t sl0 dr di dc sn0 40 ms info 0 info 0 dc 40 ms dr di tim dc pu sn0 sl0 3ms sn3t sl3t u-ref. point u-ref. point sbcx iec-q iec-q iec-q iec-q nt repeater lt s/t 3ms dr deac sl3t di dea = 0 lsl 480 ms lt-rp nt-rp dea = 0 loss of signal 480 ms res1 r epic r iom -2 r iom -2 r iom -2 r iom -2 peb 2091 pef 2091 operational description semiconductor group 139 data sheet 01.99 figure 66 loss of synchronization at repeater (nt side) itd04254 ai ai ai ai ai ar ar ai res rsy 1 lsl 1 res ei 1 du loss dr di dc 40 ms info 0 info 0 di dc lsl 40 ms dr di tim dc pu 3ms 40 ms ms 480 of sync. u-ref. point u-ref. point sbcx iec-q iec-q iec-q iec-q nt repeater lt 480 ms 3ms s/t lt-rp nt-rp sl3t sl0 sn0 sn3t sl3t sn3t sn0 sl0 480 ms r epic r iom -2 r iom -2 r iom -2 r iom -2 peb 2091 pef 2091 operational description semiconductor group 140 data sheet 01.99 figure 67 loss of signal at repeater (nt side) itd04255 ai ai ai ai ai ar ar ai res lsl 1 sl3t sn3t lsl 1 res ei1 du loss sl0 dr di dc sn0 40 ms info 0 info 0 di dc 40 ms dr di tim dc pu sn0 sl0 3ms 40 ms sn3t sl3t ms 480 of signal u-ref. point u-ref. point sbcx iec-q iec-q iec-q iec-q nt repeater lt 480 ms s/t lt-rp nt-rp 480 ms r iom -2 r iom -2 r iom -2 r iom -2 r epic peb 2091 pef 2091 operational description semiconductor group 141 data sheet 01.99 4.3.12 deactivation with repeater figure 68 deactivation with repeater itd04256 ai ai ai ai ai ar ar ai dr di dc 40 ms info 0 info 0 dc 40 ms dr di tim dc pu 3ms 40 ms u-ref. point u-ref. point sbcx iec-q iec-q iec-q iec-q nt repeater lt s/t 3ms dr deac dc di dea = 0 ar ms 3 dr deac di 3ms 40 ms lt-rp nt-rp dea = 0 sl3t sn3t sl0 sn0 sl3t sn3t sl0 sn0 sl3t sl3t dea = 0 r epic r iom -2 r iom -2 r iom -2 r iom -2 peb 2091 pef 2091 operational description semiconductor group 142 data sheet 01.99 4.3.13 activation attempt initiated by nt in nt-auto activation mode note 39: see "basic operating mode", page 50, for setting this mode. if the lt transceiver is available and ready for activation, e.g. if the lt is not in the reset or in any test state, the nt iec-q will start in this mode one single activation attempt after leaving the "test" state, i.e. after being reset. in this case activation proceeds as described in the previous sections. however, if the lt is not ready for activation, the nt will periodically start a new activation attempt every 15 seconds, till the lt side will be available and ready for activations initiated by the nt side. see "state transition diagram in nt-auto activation mode", page 162. 4.3.14 activation in the p-nt mode note 40: this function is only available if the nt mode in conjunction with the microprocessor mode (pmode = "1") are used. note also that if the iom ? -2 clock disable mode is set (see "iom ? -2 enable/disable mode", page 53) activation in p nt mode without iom ? -2 will not be possible. in some nt and te applications in the p mode, the iom ? -2 interface is functionally not needed (e.g. inband signaling, some pc card applications etc.). in such cases it is possible to control the internal state of the pin din via the msb of the ciwu register (see "ciwu-register", page 217). setting the spu (software power up) bit to "0" in the nt mode will cause the din signal to be set internally to "0", regardless of the value of the pin din. setting the spu bit to "1", which is the default value after reset, will set the pin din transparent to the internal circuit, see figure 69 below. figure 69 din control via ciwu:spu in nt p mode example for activation with p assumption: the c/i-channel is being controlled via p (i.e., swst:ci=1, see "c/i channel access", page 100). din p interface transceiver core ciwu:spu= 1 default iec-q din p interface transceiver core ciwu:spu= 0 iec-q gnd peb 2091 pef 2091 operational description semiconductor group 143 data sheet 01.99 to activate the iec-q in nt mode from power down without external control of the pin din the following procedure has to be used: ? set the spu bit to "0" in the ciwu-register (see "ciwu-register", page 217) ? write c/i-command "tim" (0 h ) ? read the ciru register after receiving the ista:cicu interrupt and verify that the c/i code "pu" (7 h ) has been indicated ? write the c/i-command "ar" (8 h ) in combination with setting the spu bit to "1" in the ciwu register 4.3.15 upstream wake-up indication in the lt repeater mode in repeater applications the iom ? -2 clocks are usually delivered by the nt repeater (see "repeater modes", page 87). in power down the iom ? -2 clock will be shut down. during power down the reception of a wake up tone from downstream will therefore not be indicated on c/i channel in upstream direction. the iec-q is equipped with an internal wake up detection function which doesnt depend on iom ? -2 1) . in the deactivated state of the lt repeater mode the pin dout will be clamped to "0" if a wake-up tone from down stream is detected and if no monitor channel command is active or pending (in both up and down stream directions) 2) . this allows connecting pin dout of the lt repeater directly to pin din of the nt repeater, and activation initiated by the te will be carried out without restrictions, as figure 70 below and the example thereafter show. . figure 70 wake up indication in repeater power down 1) note that the 15.36 mhz master clock will still be required. version 5.3 provides such a clock on pin cls in the nt repeater mode. refer to "nt repeater", page 88 2) to achieve this, all monitor channel commands and indications of the lt repeater should be completed before the nt repeater enters the power down state 10 khz wake up tone iec-q nt-rp iec-q lt-rp dout din du clamp to "0" u interface u interface upstream peb 2091 pef 2091 operational description semiconductor group 144 data sheet 01.99 example: repeater activation initiated by the terminal ? nt and lt repeater are in power down. no monitor channel command is active or pending. ? a wake-up tone is received from downstream. ? the lt repeater pulls dout low which is detected by the nt repeater on din. ? the nt repeater activates the iom ? -2 interface (see "state transition diagram nt-repeater mode", page 175). ? the lt repeater moves to the awake state and dout will be released to indicate ar on the c/i channel. note that the c/i command dc must be given on din (see "state transition diagram lt-repeater mode", page 174). ? activation takes now place as described in "activation initiated by te with repeater", page 136. peb 2091 pef 2091 operational description semiconductor group 145 data sheet 01.99 4.4 state machines 4.4.1 state machine notation rules the state machine includes all information necessary for the user to understand and predict the activation/deactivation status of the iec-q. the information contained in a state bubble is: C state name C u-signal transmitted C overhead bits transmitted C c/i-code transmitted C transition criteria C timers figure 71 state diagram notation the following example explains the use of a state diagram by an extract of the lt state diagram. the state explained is the "deactivated" state in lt mode. the state may be entered by either of three methods: C from state "receive reset" after time t7 has expired (t7 e xpired ) C from state "tear down" after the internal transition criterion "lsu" is fulfilled C from state "test" after the c/i-command "dr" has been sent downstream the following information is transmitted: C sl0 is sent on the u-interface (no signal, see "u-interface signals", page 125) C no overhead bits are sent C c/i-message "di" is issued on upstream the state may be left by either of the following methods: itd04257 state name single bit transmitted to u-interface signal transmitted to u-interface (general) indication transmitted on c/i-channel (dd) in out peb 2091 pef 2091 operational description semiconductor group 146 data sheet 01.99 C leave for state "awake" after nt wake up tone (tn) was detected and the c/i-code dc is present in the downstream direction C leave for state "alerting" after c/i-commands "ar", "arx", "ar0" or "uar" and not tn were received C leave for state "reset for loop" after c/i-command "arl" was received combinations of transition criteria are possible. logical "and" is indicated by "&" (tn & dc), logical "or" is written "or" and for a negation "/" is used. the start of a timer is indicated with "txs" ("x" being equivalent to the timer number). timers are always started when entering the new state. the action resulting after a timer has expired is indicated by the path labelled "txe". the sections following the state diagram contain detailed information about all states and signals used. these details are mode dependent and may differ for identically named signals/states. they are therefore listed for each mode. cold and warm starts two types of start-up procedures are supported by the iec-q: cold starts and warm starts. cold starts are performed after a reset and require all echo and equalizer coefficients to be recalculated. this procedure typically is completed after 1-7 seconds depending on the line characteristics. cold starts are recommended for activations where the line characteristics have changed considerably since the last deactivation. a warm start procedure uses the coefficient set saved during the last deactivation. it is therefore completed much faster (maximum 300 ms). warm starts are however restricted to activations where the line characteristics do not change significantly between two activations. regarding the path in the transition diagram, cold starts have in particular that the iec-q has entered the state test (e.g. due to a reset) prior to an activation. the activation procedure itself is then identical in both cases. therefore, the following sections apply to both warm and cold starts. 4.4.2 state machine in lt modes this section is applicable for the following lt modes: C lt mode (512 khz C 4096 khz) C cot 512 mode (512 khz) C cot 1536 mode (1536 khz) peb 2091 pef 2091 operational description semiconductor group 147 data sheet 01.99 4.4.2.1 lt modes state diagram figure 72 state transition diagram in lt modes sl0 - deactivated di tl - alerting di sl0 - awake ar sl0 - wait for tn di ei3 sl1 - ec-training ar sl2 a=0,d=1 ec-converged arm sl2 a=0,d=1 eq-training ei3 arm sl3t a=0,d=1 loss of signal lsl sl3t a=0,d=0 pend. deactivation deac sl3t a=0,d=1 loss of synchr. rsy sl0 - receiver reset lsl sl0 - tear down deac sl0 - tear down error ei3/rsy sl0 - reset for loop di sl0/sp - test hi deac dr res or res1 pin ps1=1 tn & dc (ar or ar0 or arx or uar) & /tn t1s, t2s arl t1s, t2s t2e t2s t2e t3s t2s t3e t1e t1s, t4s tn or tl (loop) t5s lsec or t4e lsec or t5e t6s sec or t6e or arl res1 res1 res1 act=1 & /ar0 t1e sai=0 & act = 0 sfd & (bbd1 or bbd0 or crcok) & (/t1e or arx) t7s res1 t10e sl3t a=1,d=1 pend. transparent uai/fj sl3t a=1,d=1 transparent a//fj ei2/fj ar0 t8e act=0 act=1 dr or lof or lsue dr or lof or lsue any state pin-dt, p-dt or dt t8s sl3t a=0,d=1 line active uai/fj sl3t a=0,d=1 s/t deactivated ar/fj uai/fj uar ar0 sai=0 sai=1 dr or lof or lsue dr or lof or lsue lsue lof t10s dr lsu t7s lsu t7e tn any state pin-ssp or pin-res or pin (ps1=1) or p-ssp or p-res or ssp or res or pfoff or ltd t4s, t1s signal to u sb to u state name ci-code indication (du) legend in out sl0 - awake error ar t9s, t4s t9e & (lsec or t4e) t1s, t5s t1s t9e & /(lsec or t4e) peb 2091 pef 2091 operational description semiconductor group 148 data sheet 01.99 4.4.2.2 transition criteria in lt modes the transition criteria used by the iec-q are described in the following sections. they are grouped into: C c/i-commands Cpin states C events related to the u-interface Ctimers c/i-commands ar activation request the iec-q is requested to enter the power-up state and to start an activation procedure by sending the wake-up signal tl. ar0 activation request with "act" bit = (0) the iec-q is requested to enter the power-up state and to start an activation procedure by sending the wake-up signal tl. after "eq training" the state "line active" will be entered independent of the "act" bit. evaluation of the "act" bit is disabled when ar0 is received and enabled when ar is received. arx activation request extended the iec-q is requested to enter the power-up state and to start an activation procedure by sending the wake-up signal tl. after "eq training" the state "line active" will be entered independently of the timer t1, i.e. if the signal sn3 has been received correctly by the lt the "line active" state will be entered, even if the t1 timer has expired. note however that if the t1 timer expires in "eq training" the c/i code ei3 will still be issued and should be ignored by the control unit upstream. arl activation request local loop-back the iec-q is requested to operate an analog loop-back (close to the u-interface) and to start the start-up sequence by sending the wake-up tone tl. this command may be issued only after the iec-q has been set to the "deactivated" state (c/i-channel code di issued on dout) and has to be issued continuously as long as loop-back is requested. dc deactivation confirmation this command enables transition from the deactivated state to the awake state, if an awake tone has been detected. if this command is not given in the transmission to the awake state is disabled. however awake tones from downstream will still be recognized and latched. for more information refer also to note 42, page 153. in the u-only activation mode the dc command can be used by the control unit on the lt side to achieve transmission transparency when the terminal peb 2091 pef 2091 operational description semiconductor group 149 data sheet 01.99 initiates an activation request. this can be done in the following manner - assumption: the iec-q on the lt side is in the "s/t deactivated" state. it receives sai=0 from the nt side, i.e. the terminal is deactivated. the control unit on the lt side issues the c/i command uar. the iec-q on the lt side issues the c/i indication uai. - the terminal initiates an activation requests, i.e. it issues the c/i command "ar" on the nt side. this causes the iec-q on the nt side to transmit sai=1 on u. - upon detection of sai=1 the iec-q on the lt side issues the c/i indication ar. - the control unit on the lt side can now issue the c/i command dc. this causes the iec-q on the lt side to reflect the polarity of the sai bit on the uoa bit (see also "signals on u-interface", page 156). i.e., the iec-q on the lt side transmits uoa=1 on u. - upon reception of uoa=1 the iec-q on the nt side transmits act=1 to u if it is controlled as given in the nt state machine (see "nt modes state diagram", page 161 ff.). transparency can now be achieved in the usual manner. dr deactivation request this command requests the iec-q to start a deactivation procedure by setting the dea bit to "0" and to cease transmission afterwards. the dr-code is a conditional command causing the iec-q only to react in the states "test", "s/t deactivated", "line active", "pending transparent" and "transparent", i.e. when the c/i-channel codes deac, uai, ar, ai, fj or ei2 are issued on dout. dt data through this unconditional command is used for test purposes only and forces the iec-q into the transparent state independent of the wake-up protocol. a far-end transceiver needs not to be connected; in case a far-end transceiver is present it is assumed to be in the same condition. note however that the c/i indication (initiated by the iec-q) in this case depends on the state of the far-end transceiver and is not specified. ltd lt disable this is an unconditional command which requests the iec-q to switch-off the remote-power-feed circuit for the subscriber line by activating the pin diss. the iec-q is transferred to the "test" state; the receiver will not be reset. peb 2091 pef 2091 operational description semiconductor group 150 data sheet 01.99 res reset unconditional command which resets the transceiver core (see "reset behavior", page 94). for cold start the reset code should be applied for a period of at least 8 iom ? -2-frames (1 ms). in lt modes the dcl clock signal needs to be applied during reset. res1 reset 1 the reset 1 command resets all receiver functions; especially the ec- and eq-coefficients and the agc are set to zero. it resets also the awake signal detection. the res1-code does not reset iom ? -2-functions (e.g. monitor channel procedure or power controller interface). the res1-code should be used when the iec-q has entered a failure condition (expiry of timer t1, loss of framing or loss of signal level) indicated by the c/i-channel ei3, rsy or lsl on dout. besides resetting the receiver, this command stops transmission on the u-interface. the dea bit is not set to "0" by res1. ssp send single pulses unconditional command which requests the transmission of single pulses on the u-interface. the pulses are issued at 1.5 ms intervals and have a duration of 12.5 m s. the chip is transferred to the "test" state; the receiver will not be reset. uar partial activation request (u only) the iec-q is requested to enter power-up state and to start an activation procedure of the u-interface only. pins pin-res pin-reset corresponds to a low level at pin res . resets the transceiver core and all registers except for register stcr in the microprocessor mode (see "reset behavior", page 94). the c/i-message deac will be issued. the duration of the reset pulse must be 30 ns minimum. the reset will be carried out only after the iom ? -2 clocks are issued. pin-ssp pin-send single pulses applies only in stand-alone mode. corresponds to a high level at pin tsp. the function of this pin is the same as for the c/i-code ssp. the c/i-message deac will be issued. the high level needs to be applied continuously for the transmission of single pulses. pin-dt pin-data through applies only in stand-alone mode. entered when both res and tsp are active (res = "0" and tsp = "1"). the function is identical with the c/i-code dt. peb 2091 pef 2091 operational description semiconductor group 151 data sheet 01.99 pin-pfoff power feed off corresponds to pin ps1 being activated. this pin indicates that the remote-power-feed circuit for the subscriber line has been turned off. the iec-q is requested to forward this indication making use of the c/i-channel code hi. the chip is transferred to the "test" state; the receiver will be reset. note 41: if one of the pin configurations pin-reset, pin-ssp or pin-dt is being used, c/i command (especially res, ssp or dt) will not be executed, i.e. pin setting has higher priority than c/i channel setting. microprocessor p-ssp p-send single pulses applies only in microprocessor mode. corresponds to the setting: stcr:tm1 = 1 and stcr:tm2 = 1. the function of this pin is the same as of the c/i-code ssp. c/i-message dr will be issued. see "test modes", page 52. p-dt p-data through applies only in microprocessor mode. this function is activated by setting: stcr:tm1 = 0 and stcr:tm2 = 1. the function of this pin is the same as of the c/i-code dt. see "test modes", page 52. u-interface events act = 0/1 "act" bit received from the nt side. C act = 1 signals that the nt has detected info3 on the s/t-interface and indicates that the complete basic access system is synchronized in both directions of transmission. the lt side is requested to provide transparency of transmission in both directions and to respond with setting the act-bit to "1". in the case of loop-backs (loop-back 2 or single-channel loop-back in the nt), however, transparency is required even when the nt is not sending act = 1. transparency is achieved in the following manner: C the iec-q performs transparency in both directions of transmission after the receiver has achieved synchronization (state eq-training is left) independent of the status of the received act-bit. C the status "ready for sending" is reached when the state transparent is entered i.e. when the c/i-channel indication ai is issued. this is valid in the case of a normal activation procedure for call control. in the case of loop-backs (loop-back 2 or single-channel loop-back in the nt and analog loop-back in the lt) however, the status "ready for sending" is reached when the state line active is entered i.e. when the c/i-channel peb 2091 pef 2091 operational description semiconductor group 152 data sheet 01.99 indication uai is issued. until the status "ready for sending" is reached, binary "0s" have to be passed in the b- and d-channels on din. C act = 0 indicates the loss of transparency on the nt side (loss of framing or loss of signal level on the s/t-interface). the iec-q informs the lt side by issuing the c/i-channel indication ei2, but performs no state change or other actions. crcok cyclic redundancy check ok this input is used as a criterion that the receiver has acquired frame synchronization and both its ec and eq coefficients have converged. lof loss of framing on the u-interface this condition is fulfilled if framing is lost for 576 ms. 576 ms are the upper limit. if the correlation between synchronization word and input signal is not optimal, lof can be issued earlier. lsec loss of signal level behind the echo canceler in the "awake" state, this input is used as indication that the nt has ceased the transmission of signal sn1. in the ec-training state, this input is used as an internal signal indicating that the ec in the lt has converged. lsu loss of signal level on the u-interface this signal indicates that a loss of signal level for the duration of 3 ms has been detected on the u-interface. this short response time is relevant in all cases where the lt waits for a response (no signal level) from the nt side, i.e. after a deactivation procedure has been started or after loss of framing in the lt occurred. lsue loss of signal level on the u-interface (error condition) after a loss of signal level has been noticed, a 492 ms timer is started. after this timer has elapsed, the lsue-criterion is fulfilled. this long response time (see also lsu) is valid in all cases where the lt is not prepared to lose signal level. note that 492 ms represent a minimum value; the actual loss of signal might have occurred earlier, e.g. when a long loop is cut at the lt side, the echo coefficients need to be readjusted to new parameters. only after the adjusted coefficient cancel the echo completely, the loss of signal is detected and the timer can be started (if the long loop is cut at the remote end, the coefficients are still correct and a loss of signal will be detected immediately). sec signal level behind the echo canceler this signal indicates that a signal level corresponding to sn2 from the nt has been detected on the u-interface. sfd superframe detected peb 2091 pef 2091 operational description semiconductor group 153 data sheet 01.99 tn tone (wake-up signal) received from the nt. when in the "deactivated" state, the iec-q is requested to start an activation procedure and to inform the lt side making use of the c/i-channel code ar. when in the "wait for tn" state, the signal tn sent by the nt acknowledges the receipt of a wake-up signal tl from the lt. when an analog loop-back is operated, the wake-up signal tl sent by the lt-transmitter is detected by the lt receiver. the tn-criteria is fulfilled when 12 consecutive periods of the 10 khz wake-up tone were detected. note 42: transition from state deactivated to state awake will only be done if the c/i command dc is issued in downstream direction, as indicated in the state diagram. however, the wake-up tone will still be detected and latched by the iec-q even if the c/i command dc is not present. in this case the iec-q will not react to the c/i commands ar, ar0, arx and uar. furthermore, if the dc command is issued later on, the iec-q will activate immediately. if a previously received wake-up tones should be ignored, e.g. because it is "old" and no more valid, the user might want to reset the wake-up tone before further action. this can be done with any kind of reset (see "reset behavior", page 94). the wake-up tone can also be reset by the c/i command res1, if it is applicable (state dependent). bbd0/1 binary "0" or "1s" detected in the b- and d-channels this internal signal indicates that for a period of time of 6C12 ms a continuous stream of binary "0s" or "1s" has been detected. it is used as a criterion that the receiver has acquired frame synchronization and both its ec- and eq-coefficients have converged. bbd1 corresponds to the signals sn2 or sn3 in the case of a normal activation and bbd0 corresponds to the internally received signal sl2 in the case of an analog loop-back or possibly a loop-back 2 in the nt. timers the start of timers is indicated by txs, the expiry by txe. table 29 below shows which timers are used in lt modes: peb 2091 pef 2091 operational description semiconductor group 154 data sheet 01.99 4.4.2.3 output signals and indications in lt modes signals and indications are issued on the iom ? -2-interface (c/i-codes) and u-interface (predefined u-signals). c/i-indications ai activation indication this indication signals that "act" = 1 has been received and that timer t8 has elapsed. this indication is not issued in case ar0 is applied or an analog loop-back is operated. ar activation request the ar-code signals that a wake-up signal has been received and that a start-up procedure has commenced. receiver synchronization has not yet been achieved. when already partially active (u only activation), ar indicates that the "sai" bit was set to (1), i.e. the s/t-interface has become active. deac deactivation this indication is issued in response to a dr-code (pend. deactivation, tear down) and in the "test" state (unless pfoff is active, i.e. ps1 = (1)). table 29 timers for lt state machine timer duration (ms) function state t1 15000 supervisor for start-up t2 3 tl-transmission receiver reset alerting reset for loop t3 40 re-transmission of tl wait for tn t4 6000 supervisor sn0 detect awake t5 1000 supervisor ec converge ec training t6 6000 supervisor sn2 detect ec converge t7 40 hold time receiver reset t8 24 delay time for ai detection pend. transparent t9 40 hold time awake error t10 40 "dea" = (0) transmission pend. deactivation peb 2091 pef 2091 operational description semiconductor group 155 data sheet 01.99 di deactivation indication idle code on the iom ? -2-interface. normally the iec-q stays in the "deactivated" state unless an activation procedure is started by the nt side. ei2 error indication 2 ei2 is issued if the received act-bit is (0). the nt receiver indicates a loss of signal or framing on the s/t-interface by setting the upstream act-bit to (0). the iec-q remains in the "transparent" state. after a signal level or framing is detected again, the c/i-indication ai will be issued anew. ei3 error indication 3 this indication is issued when the iec-q has not been able to activate successfully (expiry of timer t1). lsl loss of signal level the iec-q has entered a failure condition after loss of signal level (lsue). rsy re-synchronization indication after a loss of framing (lof) for ei3, lsl and rsy indication the lt side should react by applying the c/i-channel code res1 to allow the iec-q to enter the "receive reset" state and to reset the receiver functions. fj frame jump this indication signals that either a data buffer overflow/underflow has been detected or a phase jump of one of the iom ? -2-timing signals dcl or fsc has occurred. the fj-code is issued for a period of 1.5 ms. hi high impedance pfoff is activated which means that the remote-power-feed circuit for the subscriber line is turned off. uai u-activation indication the uai-code signals that the line system is synchronized in both directions of transmission (see also the input act = 1). maintenance bits are transmitted normally. arm activation request maintenance transmission of maintenance bits is possible. int interrupt (stand-alone mode only) a level change on input pin int triggers the transmission of this c/i code for four successive iom ? -2 frames. please refer to "interrupt", page 197 for details. peb 2091 pef 2091 operational description semiconductor group 156 data sheet 01.99 signals on u-interface the signals slx, tl and sp transmitted on the u-interface are defined in table 28, page 125. the polarity of the overhead bits act and dea is indicated as follows: a = 0/1 corresponds to act bit set to binary "0/1". d = 0/1 corresponds to dea bit set to binary "0/1". the polarity of the transmitted uoa-bit depends on the received c/i-channel code: C uar sets uoa-bit to binary 0. C ar sets uoa-bit to binary 1. C any other c/i-codes sets the uoa to the same value as the received sai bit. after deactivation the uoa-bit is set to binary 0 until a valid sai-bit is received. 4.4.2.4 lt states this section describes the functions of all states defined in lt modes. alerting the wake-up signal tl is transmitted for 3 ms (t2) in response to an activation request from the lt side (ar, ar0, uar or arl). in the case of an analog loop-back, the signal tl is forwarded internally to the wake-up signal detector and stored. awake if the c/i command is issued in the deactivated state the awake state is entered upon the receipt of a wake-up or an acknowledge signal tn from the nt. in the case of an activation started by the lt side, timer t1 is restarted when the "awake" state is entered. awake error the "awake error" state is equivalent to the "awake" state, but is entered only when a wake-up signal is received while being in the "receive reset" state. as the "receive reset" state was entered upon the application of the c/i-channel code res1, the "awake error" state assures that a minimum amount of time elapses between the application of the res1-code and the iec-q entering a state (eq training) in which it again reacts on the res1-code. the lt side is requested to stop issuing the command res1 within t9 after the receipt of the c/i-channel code ar on dout and to replace it by another command such as the idle code dc for instance. peb 2091 pef 2091 operational description semiconductor group 157 data sheet 01.99 deactivated (full reset) in the "deactivated" state the device may enter the low power consumption condition. the power-down mode is entered if no monitor messages are active or pending. in power-down the receiver and parts of the interface are deactivated while functions related to the iom ? -2-interface and the wake-up detector are still active. no signal is sent on the u-interface, the differential outputs aout and bout are set to 0 v. the iec-q waits for a wake-up signal tn from the nt side or an activation request (ar, arx, ar0, uar or arl) from the lt side to start an activation procedure. for the recognition of the wake-up signal tn the following procedure applies: C tn detected for 4 periods C> transfer within the "deactivated" state into power-up C in power-up both differential outputs are set to 3.2 v C tn detected for a total of 12 consecutive periods C> transition criterion tn fulfilled, change to next state, if in addition the c/i-command dc is issued in the downstream direction. C tn detected for more than 4 but less than 12 periods C> return to power-down the input sensitivity stated "analog characteristics", page 266, presents the minimum level required to meet the tn transition criterion. the power-up condition may thus already be entered at a lower level. note 43: refer also to note 42, page 153, for more information about device behavior when a wake-up tone tn is detected in the deactivated state. ec converged upon the ec-coefficients having converged, the iec-q starts the transmission of signal sl2 and waits for the receipt of signal sn2 from the nt (sec). if this condition is not met within t6, the start-up procedure will be continued. in the case of an analog loop-back, this state is left immediately because the ec compensates for the looped back transmit signal. ec-training the signal sl1 is transmitted on the u-interface to allow the lt receiver to update its ec-coefficients. the "ec-training" state is left when the ec has converged (lsec) or when timer t5 has elapsed. timer t5 allows the start-up procedure to proceed even if lsec could not be detected, e.g. due to a high noise level on the u-interface. eq-training the "eq-training" is left after the receiver has achieved synchronization and the superframe indication has been detected (sfd). upon expiry of timer t1 the c/i-channel indication ei3 is issued. peb 2091 pef 2091 operational description semiconductor group 158 data sheet 01.99 line active in the "line active" state, the iec-q transmits transparently in both directions. the u-interface is synchronized and the maintenance channel is operational. the iec-q stays in the line-active state C during a normal activation procedure while the "act" bit = (0) is received C when an analog loop-back is established C while c/i-command ar0 is applied downstream in the case of normal activation with call control, binary "0s" have to be applied to the b and d channels in downstream direction. after the c/i-channel indication uai has been issued, the layer-2 receiver should be fully operational to prevent the first layer-2 message issued by the nt side upon the receipt of the ali-code in the te, to be lost. loss of signal the "loss of signal" state is entered upon the detection of a failure condition i.e. loss of receive signal (lsue). the act bit is set to "0" and the c/i-channel indication lsl is issued. the iec-q waits for the c/i-channel command res1 to enter the "receive reset" state. loss of synchronization the "loss of synchronization" state is entered upon the detection of a failure condition i.e. loss of framing by the lt receiver (lof). the act-bit is set to "0" and the c/i-channel indication rsy is issued. the iec-q waits for the c/i-channel command res1 to enter the "tear down error" state and subsequently the "receive reset" state. pending deactivation "pending deactivation" is a transient state entered after the receipt of a dr-code. the dea-bit is set to "0". timer t10 assures that the dea-bit is set to "0" in at least three consecutive superframes before the transmit level is turned off. pending transparent "pending transparent" is a transient state entered upon the detection of act = 1 and left by t8. the act-bit is set to "1". the purpose of this state is to issue the c/i-channel indication ai (corresponding to "ready for sending") 24 ms after the act-bit has been set to "1" by the lt-transceiver. this assures that under normal operating conditions the ai-indication is issued first on the te side and only afterwards on the lt side. thus the layer-2 receiver in the te is already operational when the first layer-2 message is issued by the lt side. peb 2091 pef 2091 operational description semiconductor group 159 data sheet 01.99 reset for loop "reset for loop" resets the receiver in order to guarantee a correct adaption of the echo- and equalizer coefficients. receive reset the "receive reset" state assures that for a period of t7 no signal, especially no wake-up signal tl, is sent on the u-interface, i.e. no activation procedure is started from the lt side. a wake-up signal tn, however, from the nt side is acknowledged. s/t deactivated the state "s/t deactivated" will be entered if the received act- and sai-bits are set to (0). in this state the signal sl3t, act = (0), dea = (1) and uoa = (0) are transmitted downstream. the c/i-code uai is issued upstream while the received sai = (0). in order to initiate a complete activation from the s/t deactivation state, the lt needs to set the uoa-bit to (1). this will occur if either of the following three conditions are met: C c/i = ar (lt activation) C sai = (1) & ar (te activation with exchange control [c/i uar downstream]) C sai = (1) (te activation without exchange control [c/i dc downstream]) "s/t deactivated" will be left if the received act bit is (1), or the c/i code ar0 is applied. tear down in "tear down" state, transmission ceases in order to deactivate the basic access, and the iec-q waits for a response (no signal level, lsu) from the nt side. tear down error "tear down error" state is entered after loss of framing has been detected. transmission ceases in order to deactivate the basic access and the iec-q waits for a response (no signal level, lsu) from the nt side. ei3-indication is transmitted after a transition forced by res1 from the wait-for-tn or eq-training states. in the case of transition from the "loss of synchronization" state rsy is sent. peb 2091 pef 2091 operational description semiconductor group 160 data sheet 01.99 test this "test" mode is entered when the unconditional commands res, ssp, ltd, pin-res, pin-ssp or pfoff are used. it is left when the pins resq, tsp and ps1 are inactive and the c/i-channel code dr is received. the output signals are as follows: C when the c/i-channel code res or res1 is applied or when the pin resq is activated: sl0 and deac C when the c/i-channel code ssp is applied or when the pin tsp is activated: single pulses (sp) and deac C when the c/i-channel code ltd is applied: sl0 and deac; furthermore, the pin diss is activated C when the pin ps1 is activated: sl0 and hi in this state the iec-q does not react to the receipt of a wake-up signal tn. transparent this "transparent" state corresponds to the fully active state in the case of a normal activation for call control. it may also be entered in the case of a loop-back 2 if the nt issues act = 1 or in case of a single-channel loop-back in the nt. the lt side is informed that the status "ready for sending" is reached (indication ai). if the nt side loses transparency (receipt of act = 0), the lt side is informed by making use of the c/i-channel indication ei2, but no state change is performed. if the s/t-interface is deactivated (sai = (0) & act = (0)), the device is transferred to the s/t deactivated state. wait for tn in "wait for tn" the iec-q waits for a response (tone tn from the nt or tone tl in case of an analog loop-back) to the transmission of the wake-up signal tl. if no response is received within t3, the state is left for re-transmission of a wake-up tone tl. this procedure is repeated until the detection of tone tn or until expiry of timer t1. in this case the c/i-channel indication ei3 is issued, but no state change is performed. 4.4.3 state machine in nt modes this chapter describes the behavior of the iec-q device if operated in either of the following nt modes: C nt mode (512 khz) C nt-pbx mode (512 C 4096 khz) C te mode (1536 khz) C nt-auto activation mode (512 khz) figure 73 describes the behavior of the first three modes, and figure 74 describes the behavior of the last one. peb 2091 pef 2091 operational description semiconductor group 161 data sheet 01.99 4.4.3.1 nt modes state diagram figure 73 state transition diagram in nt, te and nt-pbx modes sn0 - deactivated dc sn0 - iom ? awaked pu tn - alerting dc pu sn1 - ec-training dc sn0 - eq-training dc sn2 - wait for sf dc sn3/sn3t act=0 synchronized 1 dc/fj act=0 synchronized 2 ar/arl/fj sn3/sn3t act=1 wait for act ar/arl/fj sn3/sn3t sn3t act=1 transparent ai/ail/fj sn3t act=0 error s/t ar/arl/fj sn0 - pending timing dc sn0/sp - test dr sn1 - ec-training al dc sn3 act=0 wait for sf al dc sn3t act=0 analog loop back ar/fj sn0 - pend. receiver res. ei1 sn0 - receicer reset dr tn - alerting 1 dr sn1 - ec-training 1 dr sn3 act=1/0 pend. deact. s/t dr sn3t act=1 pend. deact. u dc uoa=1 ? tim or (din=0) or (spu=0) t1s, t11s ar or tl t14e tl di t14s ar or tl t1s,t11s di t14s di lsec or t12e bbd1 & sfd t12s arl t12s t11e lsec or t12e bbd0 & fd bbd0 & sfd t12s t11e (lsec or t12e) & di di uoa=1 t1e t1e lof lof lof lof lof lof lof ai act=1 act=0 act=1 & ai ei1 ei1 act=0 lsu or (/lof & t13e) t7s lsue lsue lsue lsue lsue dea=0 dea=0 dea=0 dea=0 dea=0 dea=0 lsue dea=1 uoa=0 no uoa=0 uoa=0 uoa=0 yes tl any state pin-dt, p-dt or dt any state pin-ssp or pin-res or p-ssp or p-res or ssp or res t1s,t11s signal to u sb to u state name ci-code indication (dd) legend in out t14s t13s t7s t7e & di lsu /lsec & /t12e & di peb 2091 pef 2091 operational description semiconductor group 162 data sheet 01.99 figure 74 state transition diagram in nt-auto activation mode sn0 - deactivated dc sn0 - iom ? awaked pu tn - alerting dc pu sn1 - ec-training dc sn0 - eq-training dc sn2 - wait for sf dc sn3/sn3t act=0 synchronized 1 dc/fj act=0 synchronized 2 ar/arl/fj sn3/sn3t act=1 wait for act ar/arl/fj sn3/sn3t sn3t act=1 transparent ai/ail/fj sn3t act=0 error s/t ar/arl/fj sn0 - pending timing dc sn0/sp - test dr sn1 - ec-training al dc sn3 act=0 wait for sf al dc sn3t act=0 analog loop back ar/fj sn0 - receicer reset dr tn - alerting 1 dr sn1 - ec-training 1 dr sn3 act=1/0 pend. deact. s/t dr sn3t act=1 pend. deact. u dc uoa=1 ? tim or (din=0) or (spu=0) t1s, t11s ar or tl t14e tl di t14s ar or tl t1s,t11s di lsec or t12e bbd1 & sfd t12s arl t12s t11e lsec or t12e bbd0 & fd bbd0 & sfd t12s t11e (lsec or t12e) & di di uoa=1 lsue or t1e t1e lof lof lof lof lof lof lof ai act=1 act=0 act=1 & ai ei1 ei1 act=0 lsue lsue lsue lsue lsue dea=0 dea=0 dea=0 dea=0 dea=0 dea=0 lsue dea=1 uoa=0 no uoa=0 uoa=0 uoa=0 yes tl any state pin-dt, p-dt or dt any state pin-ssp or pin-res or p-ssp or p-res or ssp or res t1s,t11s signal to u sb to u state name ci-code indication (dd) legend in out di t14s t1s,t11s t7e & di lsu sn0 - pending alerting 1 ei1 lsu or (/lof & t13e) t13s t7s /lsec & /t12e & di peb 2091 pef 2091 operational description semiconductor group 163 data sheet 01.99 4.4.3.2 transition criteria in nt modes c/i-commands ai activation indication the s-transceiver issues this indication to announce that the s-receiver is synchronized. the iec-q informs the lt side by setting the "act" bit to "1". ar activation request info1 has been received by the s-transceiver or the intelligent nt wants to activate the u-interface. the iec-q is requested to start the activation process by sending the wake-up signal tn. arl activation request local loop-back the iec-q is requested to operate an analog loop-back (close to the u-interface) and to begin the start-up sequence by sending sn1 (without starting timer t1). this command may be issued only after the iec-q has been reset by making use of the c/i-channel code res or a hardware reset. this assures that the ec- and eq-coefficients updating algorithms converge correctly. the arl-command has to be issued continuously as long as the loop-back is required. di deactivation indication this indication is used during a deactivation procedure to inform the iec-q that timing signals are needed no longer and that the iec-q may enter the deactivated (power-down) state. the di-indication has to be issued until the iec-q has answered with the dc-code. din = 0 binary "0" polarity on din this asynchronous signal requests the iec-q to provide iom ? -2 clocks. hereafter, binary "0s" in the c/i-channel (code tim "0000" or any other code different from di "1111") keep the iom ? -2 interface active. dt data through this unconditional command is used for test purposes only and forces the iec-q into a state equivalent to the "transparent" state. the far-end transceiver is assumed to be in the same condition. note however that in this case the c/i indication (initiated by the iec-q) depends on the state of the far-end transceiver and is not specified. ei1 error indication 1 the s-transceiver indicates an error condition on its receiver side (loss of frame alignment or loss of incoming signal). the iec-q informs the lt side by setting the act-bit to "0" thus indicating that transparency has been lost. peb 2091 pef 2091 operational description semiconductor group 164 data sheet 01.99 res reset unconditional command which resets the transceiver core (see "reset behavior", page 94). especially the ec- and eq-coefficients are set to zero. ssp send single pulses unconditional command which requests the transmission of single pulses on the u-interface. the pulses are issued at 1.5 ms intervals and have a duration of 12.5 m s. the chip is in the "test" state, the receiver will not be reset. tim timing in the nt mode the iec-q is requested to continue providing timing signals and not to leave the "power-up" state. pins pin-res pin-reset corresponds to a low level at pin res . resets the transceiver core and all registers except for register stcr in the microprocessor mode (see "reset behavior", page 94). c/i-message deac will be issued. the duration of the reset pulse must be 30 ns minimum. pin-ssp pin-send single pulses applies only in stand-alone mode. corresponds to a high-level at pin tsp in stand-alone mode. the function of this pin is the same as of the c/i-code ssp. c/i-message dr will be issued. the high-level must be applied continuously for single pulses. pin-dt pin-data through applies only in stand-alone mode. this function is activated when both pins res and tsp are active (res = 0 and tsp = 1). the function of this pin is the same as of the c/i-code dt. note 44: if one of the pin configurations pin-reset, pin-ssp or pin-dt is being used, c/i command (especially res, ssp or dt) will not be executed, i.e. pin setting has higher priority than c/i channel setting. microprocessor spu=0 this condition applies only in the microprocessor mode. setting the ciwu:spu (software power up) bit to "0" in the nt mode will cause the din signal to be set internally to "0", regardless of the value of the pin din. see "activation in the p-nt mode", page 142. peb 2091 pef 2091 operational description semiconductor group 165 data sheet 01.99 p-ssp p-send single pulses applies only in microprocessor mode. corresponds to the setting: stcr:tm1 = 1 and stcr:tm2 = 1. the function of this setting is the same as of the c/i-code ssp. c/i-message dr will be issued. see "test modes", page 52. p-dt p-data through applies only in microprocessor mode. this function is activated by setting: stcr:tm1 = 0 and stcr:tm2 = 1. the function of this setting is the same as of the c/i-code dt. see "test modes", page 52. u-interface events the signals slx and tl received on the u-interface are defined in table 28, page 125. act act-bit received from lt side. C act = 1 requests the iec-q to transmit transparently in both directions. as transparency in receive direction (u-interface to iom ? -2) is already performed when the receiver is synchronized, the receipt of act = 1 establishes transparency in transmit direction (iom ? -2 to u-interface), too. in the case of loop-backs, however, transparency in both directions of transmission is established when the receiver is synchronized. C act = 0 indicates that the lt side has lost transparency. dea dea-bit received from the lt side C dea = 0 informs the iec-q that a deactivation procedure has been started by the lt side. C dea = 1 reflects the case when dea = 0 was detected by faults due to e.g. transmission errors and allows the iec-q to recover from this situation (see state pend. deact. u). uoa uoa-bit received from network side C uoa = 0 informs the iec-q that only the u-interface is to be activated. the s/t-interface must remain deactivated. C uoa = 1 enables the s/t-interface to activate. lof loss of framing on the u-interface this condition is fulfilled if framing is lost for 576 ms. 576 ms are the upper limit. if the correlation between synchronization word and the input signal is not optimal, lof may be issued earlier. lsec loss of signal level behind the echo canceler internal signal which indicates that the echo canceler has converged. peb 2091 pef 2091 operational description semiconductor group 166 data sheet 01.99 lsu loss of signal level on the u-interface this signal indicates that a loss of signal level for a duration of 3 ms has been detected on the u-interface. this short response time is relevant in all cases where the nt waits for a response (no signal level) from the lt side, i.e. after a deactivation has been announced (receipt of dea = 0), after the nt has lost framing, and after timer t1 has elapsed. lsue loss of signal level on the u-interface (error condition) after a loss of signal has been noticed, a 588 ms timer is started. when it has elapsed, the lsue-criterion is fulfilled. this long response time (see also lsu) is valid in all cases where the nt is not prepared to lose signal level i.e. the lt has stopped transmission because of loss of framing, an unsuccessful activation, or the transmission line is interrupted. note that 588 ms represent a minimum value; the actual loss of signal might have occurred earlier, e.g. when a long loop is cut at the nt side and the echo coefficients need to be readjusted to the new parameters. only after the adjusted coefficients cancel the echo completely, the loss of signal is detected and the timer can be started (if the long loop is cut at the remote end, the coefficients are still correct and loss of signal will be detected immediately). sfd superframe (isw) detected on u-interface fd frame (sw) detected on u-interface tl wake-up signal received from the lt the iec-q is requested to start an activation procedure. the tl-criterion is fulfilled when 12 consecutive periods of the 10-khz wake-up tone were detected. when in the "pending timing" state and automatic activation after reset is selected (nt-auto activation mode), a recognition of tl is assumed every time the "pending timing" state has been entered from the "test" state (caused by c/i code di). this behavior allows the iec-q to initiate activation attempts after having been reset (see "activation attempt initiated by nt in nt-auto activation mode", page 142). bbd0/1 binary "0s" or "1s" detected in the b- and d-channels this internal signal indicates that for 6-12 ms, a continuous stream of binary "0s" or "1s" has been detected. it is used as a criterion that the receiver has acquired frame synchronization and both its ec- and eq-coefficients have converged. bbd0 corresponds to the signal sl2 in the case of normal activation and bbd1 corresponds to the internally received signal sn3 in case of an analog loop back in the nt mode. peb 2091 pef 2091 operational description semiconductor group 167 data sheet 01.99 timers the start of timers is indicated by txs, the expiry by txe. the table 30 shows which timers are used by the iec-q in nt mode: 4.4.3.3 output signals and indications in nt modes signals and indications are issued on the c/i channel and on the u-interface (predefined u-signals). c/i indications ai activation indication the iec-q has established transparency of transmission in the direction iom ? -2 to u-interface. in an nt1, the s-transceiver is requested to send info4 and to achieve transparency of transmission in the direction iom ? -2 to s/t-interface. ail activation indication loop-back the iec-q has detected act = 1 while loop-back 2 is still established. in an nt1, the s-transceiver is requested to send info4 (if a transparent loop-back 2 is to be implemented) and to keep loop-back 2 active. ar activation request the iec-q has synchronized on the incoming signal. in an nt1, the s-transceiver is requested to start the activation procedure on the s/t-interface by sending info2. arl activation request loop-back the iec-q has detected a loop-back 2 command in the eoc-channel and has established transparency of transmission in the direction iom ? -2 to u-interface. in an nt1, the s-transceiver is requested to send info2 (if a transparent loop-back 2 is to be implemented) and to operate loop-back 2. table 30 timers for nt state machine timer duration (ms) function state t1 15000 supervisor for start-up t7 40 hold time receive reset t11 9 tn-transmission alerting t12 5500 supervisor ec-converge ec-training t13 15000 frame synchronization pend. receive reset t14 0.5 hold time pend. timing peb 2091 pef 2091 operational description semiconductor group 168 data sheet 01.99 dc deactivation confirmation idle code on the c/i channel. the iec-q stays in the power-down mode unless an activation procedure has been started from the lt side. the u-interface may be activated but the s/t-interface has to remain deactivated. dr deactivation request the iec-q has detected a deactivation request command from the lt side for a complete deactivation or a s/t only deactivation. in an nt1, the s-transceiver is requested to start the deactivation procedure on the s/t-interface by sending info0. ei1 error indication 1 the iec-q has entered a failure condition caused by loss of framing on the u-interface or expiry of timer t1. int interrupt (stand-alone mode only) a level change on input pin int triggers the transmission of this c/i code for four successive iom ? -2 frames. please refer to "interrupt", page 197 for details. pu power up the iec-q provides iom ? -2 clocks. signals on u-interface the signals snx, tn and sp transmitted on the u-interface are defined in table 28, page 125. the polarity of the transmitted act-bit is as follows: a = 0/1 corresponds to act-bit set to binary "0/1" the polarity of the issued sai-bit depends on the received c/i-channel code: di and tim leads to sai = 0, any other c/i-code sets the sai-bit to 1 indicating activity on the s/t-interface. 4.4.3.4 nt states this section describes the functions of all states defined in nt modes: alerting the wake-up signal tn is transmitted for a period of t11 either in response to a received wake-up signal tl or to start an activation procedure on the lt side. peb 2091 pef 2091 operational description semiconductor group 169 data sheet 01.99 alerting 1 "alerting 1" state is entered when a wake-up tone was received in the "receive reset" state and the deactivation procedure on the nt side was not yet finished. the transmission of wake-up tone tn is started. analog loop-back upon detection of binary "1s" for a period of 6C12 ms and of the superframe indication, the "analog loop-back" state is entered and transparency is achieved in both directions of transmission. this state can be left by making use of any unconditional command. only the c/i-channel code res should be used, however. this assures that the ec- and eq-coefficients are set to zero and that for a subsequent normal activation procedure the receiver updating algorithms converge correctly. deactivated the deactivated state is a power-down state. if there are no pending monitor channel messages from the iec-q, i.e. all monitor channel messages have been acknowledged, the iom ? -2-clocks are turned off. no signal is sent on the u-interface. the iec-q waits for a wake-up signal tl from the lt side to start an activation procedure. to enter state iom ? -2 awake a wake-up signal (din = 0 or spu=0 in p mode) is required if the iom ? -2-clocks are disabled. the wake-up signal is provided via the iom ? -2 interface (pin din = 0 or bit spu=0 in p mode). if the iom ? -2-clocks were active in state deactivated c/i-code tim is sufficient for a transition to state iom ? -2 awake. ec training the signal sn1 is transmitted on the u-interface to allow the nt receiver to update the ec-coefficients. the automatic gain control (agc), the timing recovery and the eq updating algorithm are disabled. the "ec-training" state is left when the ec has converged (lsec) or when timer t12 has elapsed. ec-training 1 the "ec-training 1" state is entered if transmission of signal sn1 has to be started and the deactivation procedure on the nt side is not yet finished. ec-training al this state is entered in the case of an analog loop-back. the signal sn1 is transmitted on the u-interface to allow the nt receiver to update the ec-coefficients. the automatic gain control (agc), the timing recovery and the eq updating algorithm are disabled. the "ec-training" state is left when the ec has converged (lsec) or when timer t12 has elapsed. peb 2091 pef 2091 operational description semiconductor group 170 data sheet 01.99 eq-training the receiver waits for signal sl1 or sl2 to be able to update the agc, to recover the timing phase, to detect the synch-word (sw), and to update the eq-coefficients. the "eq-training" state is left upon detection of binary "0s" in the b- and d-channels for a period of 6C12 ms corresponding to the detection of sl2. error s/t loss of framing or loss of incoming signal has been detected on the s/t-interface (ei1). the lt side is informed by setting the act-bit to "0" (loss of transparency on the nt side). the following codes are issued on the c/i-channel: C normal activation or single-channel loop-back: ar C loop-back 2: arl iom ? -2 awaked timing signals are delivered on the iom ? -2 interface. the iec-q enters the "deactivated" state again upon detection of the c/i-channel code di (idle code). pending deactivation of s/t the iec-q has received the uoa-bit at zero after a complete activation of the s/t-interface. the iec-q deactivates the s/t-interface by issuing dr in the c/i-channel. the value of the act-bit depends on its value in the previous state. pending deactivation of u-interface the iec-q waits for the receive signal level to be turned off (lsu) to enter the "receiver reset" state and start the deactivation procedure. pending receive reset note 45: this state doesnt exist in nt-auto activation mode. the "pending receive reset" state is entered upon detection of loss of framing on the u-interface or expiry of timer t1. this failure condition is signalled to the lt side by turning off the transmit level (sn0). the iec-q then waits for a response (no signal level lsu) from the lt side to enter the "receive reset" state. peb 2091 pef 2091 operational description semiconductor group 171 data sheet 01.99 pending alerting 1 note 46: this state only exists in nt-auto activation mode. the "pending alerting" state is entered upon detection of loss of framing on the u-interface or expiry of timer t1. this failure condition is signalled to the lt side by turning off the transmit level (sn0). the iec-q then waits for a response (no signal level lsu) from the lt side to enter the "alerting 1" state. pending timing the pending timing state assures that the c/i-channel code dc is issued four times before the timing signals on the iom ? -2 interface are turned off. in case the nt-auto activation mode is selected the recognition of the lt wake-up tone tl is assumed every time the "pending timing" state has been entered from the "test" state. this function guarantees that the nt (in nt-auto activation mode) starts one activation attempts after having been reset, see "activation attempt initiated by nt in nt-auto activation mode", page 142. receive reset the "receive reset" state is entered upon detection of a deactivation request from the lt side, after a failure condition on the u-interface (loss of signal level lsue), or following the "pending reset" state upon expiry of timer t1 or loss of framing. no signal is transmitted on the u-interface, especially no wake-up signal tn, and the s-transceiver or microcontroller is requested to start the deactivation procedure on the nt side (dr). timer t7 assures that no activation procedure is started from the nt side for a minimum period of t7. this gives the lt a chance to activate the nt. the state is left only after completion of the deactivation procedure on the nt side (receipt of the c/i-channel code di), unless a wake-up tone is received from the lt side. synchronized 1 when reaching this state the iec-q informs the lt side by sending the superframe indication (inverted synchronization word). the loop-back commands decoded by the eoc-processor control the output of the transmit signals: C normal activation and uoa = 0: sn3 C any loop-back and uoa = 0 (no loop-back): sn3t the value of the issued sai-bit depends on the received c/i-channel code: di and tim lead to sai = 0, any other c/i-code sets the sai-bit to 1 indicating activity on the s/t-interface. the iec-q waits for the receipt of uoa = 1 to enter the "synchronized 2" state. peb 2091 pef 2091 operational description semiconductor group 172 data sheet 01.99 synchronized 2 in this state the iec-q has received uoa = 1. this is a request to activate the s/t-reference point. the loop-back commands detected by the eoc-processor control the output of indications and transmit signals: C normal activation and uoa = (1): sn3 and ar C single channel loop-back and uoa = (1): sn3t and ar C loop-back 2 (lbbd): sn3t and arl C the value of the issued sai-bit depends on the received c/i-channel code: di and tim lead to sai = 0, any other c/i-code sets the sai-bit to 1 indicating activity on the s/t-interface. the iec-q waits for the receipt of the c/i-channel code ai to enter the "wait for act" state. test the "test" mode is entered when the unconditional commands res, ssp, pin-res, pin-ssp or p-ssp are used. it is left when normal iec-q operation is selected, i.e. reset and test modes are not active, and the c/i-channel codes di or arl are received. the following signals are transmitted on the u-interface: C no signal level (sn0) when the c/i-channel code res is applied or a hardware reset is activated. C single pulses (sp) when one of the ssp commands is applied. transparent this state is entered upon the detection of act = 1 received from the lt side and corresponds to the fully active state. in the case of a normal activation in both directions of transmission the following codes are output: C normal activation or single-channel loop-back: ai C loop-back 2: ail wait for act upon the receipt of ai, the act-bit is set to "1" and the nt waits for a response (act = 1) from the lt side. the output of indications and transmit signals is as defined for the "synchronized" state. wait for sf upon detection of sl2, the signal sn2 is sent on the u-interface and the receiver waits for detection of the superframe indication. timer t1 is then stopped and the "synchronized" state is entered. peb 2091 pef 2091 operational description semiconductor group 173 data sheet 01.99 wait for sf al this state is entered in the case of an analog loop-back and allows the receiver to update the agc, to recover the timing phase, and to update the eq-coefficients. signal sn3 is sent instead of signal sn2 in the "wait-for-sf" state. 4.4.4 state machine in repeater modes state diagram the lt-rp- and nt-rp-state diagrams are subsets of the related diagrams of lt and nt modes so the meaning of events and states are mostly identical. all differences caused by special requirements of the implementation of the repeater modes are listed below. C act-, uoa-, sai- and dea-bits are completely controlled via the mon-2-messages, so they are not referenced as outputs in the state diagrams. C to enable the deactivation of the first section in case of an erroneous situation in the second section of the u-interface, a new c/i-channel code is introduced. du (0011) leads to the deactivation of the nt-rp passing to "receive reset". C the mon-2-message is accepted and stored at any time except during reset (pin or c/i-channel command). note 47: in repeater applications it is recommended to use the eoc transparent mode. this implies that the c/i indications arl and ail are not issued upon reception of the eoc command lbbd from upstream in the states synchronized, transparent and error s/t of the nt-rp state diagram (see "state transition diagram nt-repeater mode", page 175). for handling eoc commands in repeater mode, see "eoc addressing management", page 257. in non standard applications of the nt repeater mode the c/i indications arl and ail will be issued if the eoc auto mode is being used and if the eoc command lbbd has been received from upstream. peb 2091 pef 2091 operational description semiconductor group 174 data sheet 01.99 figure 75 state transition diagram lt-repeater mode sl0 - deactivated di tl - alerting di sl0 - awake ar sl0 - wait for tn di ei3 sl1 - ec-training ar sl2 - ec-converged arm sl2 - eq-training ei3 arm sl3t - loss of signal lsl sl3t - pend. deactivation deac sl3t - loss of synchr. rsy sl0 - receiver reset lsl sl0 - tear down deac sl0 - tear down error ei3/rsy sl0 - reset for loop di sl0/sp - test hi deac dr res or res1 pin ps1=1 tn & dc (ar or ar0 or arx or uar) & /tn t1s, t2s arl t1s, t2s t2e t2s t2e t3s t2s t3e t1e t1s, t4s tn or tl (loop) t5s lsec or t4e (ar or arl) & (lsec or t5e) t6s sec or t6e or arl res1 res1 res1 t1s t1e sfd & (bbd1 or bbd0 or crcok) t7s res1 t10e sl3t - pend. transparent uai/fj sl3t - transparent a//fj ei2/fj t8e any state pin-dt, p-dt or dt t8s lsue lof t10s dr lsu t7s lsu t7e tn any state pin-ssp or pin-res or pin (ps1=1) or p-ssp or p-res or ssp or res or pfoff or ltd lsue lof dr signal to u sb to u state name ci-code indication (du) legend in out sl0 - awake error ar t9s, t4s t9e & (lsec or t4e) t1s, t5s t1s t9e & /(lsec or t4e) peb 2091 pef 2091 operational description semiconductor group 175 data sheet 01.99 figure 76 state transition diagram nt-repeater mode 1) refer to note 47: on page 173 sn0 - deactivated dc sn0 - iom ? awaked pu tn - alerting dc pu sn1 - ec-training dc sn0 - eq-training dc sn2 - wait for sf dc - synchronized ar/arl 1) sn3/sn3t sn3t - transparent ai/ail 1) sn3t - error s/t ar/arl 1) sn0 - pending timing dc sn0/sp - test dr sn1 - ec-training al dc sn3 - wait for sf al dc sn3t - analog loop back ar/fj sn0 - pend. receiver res. ei1 sn0 - receicer reset dr tn - alerting 1 dr sn1 - ec-training 1 dr sn3t - pend. deact. u ar tim or (din=0) or (spu=0) t1s, t11s ar or tl t14e tl di t14s ar or tl t1s,t11s di t14s di lsec or t12e bbd1 & sfd t12s arl t12s t11e lsec or t12e bbd0 & fd bbd0 & sfd t12s t11e (lsec or t12e) & di t1e t1e du or lof du or lof du or lof lof ai ai ei1 lsu or (/lof & t13e) t7s lsue lsue lsue dea=0 dea=0 dea=0 dea=1 tl any state pin-dt, p-dt or dt any state pin-ssp or pin-res or p-ssp or p-res or ssp or res t1s,t11s signal to u - state name ci-code indication (dd) legend in out t14s t13s t7s t7e & di lsu di peb 2091 pef 2091 operational description semiconductor group 176 data sheet 01.99 4.5 monitoring transmission quality the basic tool for monitoring transmission quality is the cyclic redundancy check procedure (see "cyclic redundancy check (crc)", page 64). calculation verification and insertion of the crc bits are performed automatically by the iec-q and there is no possibility to directly control this procedure, or access the crc bits. nevertheless, the iec-q provides several methods for monitoring crc failures and crc procedure function. this will be discussed in this chapter. for an overview of crc violation indications on both lt and nt sides, see figure "crc violation indications", page 184. definitions nebe: for the 2b+d and m4 bits received from the u-interface the check sum will be calculated by the crc processor and compared with the crc bits received in the successive superframe (see "u-frame structure", page 68, for definition of data position in the u-interface). a "near end block error" (nebe) occurs if these two values are not identical. in other words C nebe (lt side) error during transmission from nt to lt C nebe (nt side) error during transmission from lt to nt if a nebe has been detected the bit febe of the next u superframe available for transmission is set to 0. febe: a "far end block error" (febe) is detected if the febe bit of the received from the u-interface is set to 0. in other words C febe (lt side) error during transmission from lt to nt C febe (nt side) error during transmission from nt to lt note 48: near-end block errors and far end block errors correspond to bit errors occurred in the superframe preceding the last completed one. this is due to the fact that the crc sum of a superframe, say sf(1), is transmitted in the next superframe sf(2), i.e. a comparison between the calculated sum and the received sum can only be performed if the superframe containing the check sum, sf(2), has been completely received. figure 77 shows this relationship for the crc and the febe bits. peb 2091 pef 2091 operational description semiconductor group 177 data sheet 01.99 figure 77 relationship between crc and febe bits and superframe number nebe indications in nt and lt-rp modes each nebe will be indicated in the following way C the mon-1 message nebe is issued via iom ? -2 and p interface if only a nebe occurred C the mon-1 message fnbe is issued via iom ? -2 and p interface if nebe and a febe occurred simultaneously for informations about mon-1 structure and codes, see "mon-1 codes", page 227. note 49: in lt and cot modes a nebe will not be actively indicated by the iec-q. to monitor nebe violations the nebe counter should be read out, see "block error counters", page 178. febe indications in nt and lt-rp modes each febe will be indicated in the following way C the mon-1 message febe is issued via iom ? -2 and p interface if only a febe have occurred C the mon-1 message fnbe is issued via iom ? -2 and p interface if nebe and a febe have occurred simultaneously for informations about mon-1 structure and codes, see "mon-1 codes", page 227. lt --> nt superframe frame number ...z a b c d current crc bits related to frame number zabc current febe bit related to frame number 012 nt --> lt superframe frame number ...0 1234 current crc bits related to frame number 0123 current febe bit related to frame number zab peb 2091 pef 2091 operational description semiconductor group 178 data sheet 01.99 note 50: in lt and cot modes a febe will not be actively indicated by the iec-q. to monitor nebe violations the nebe counter should be read out, see "block error counters", page 178. note also that although the febe bit is part of the mon-2 indication, a change of the single bit febe alone (i.e. if all other single bits didnt change) will not initiate a mon-2 indication in any filtering method setting of single bits indications, see "single bits reception from u", page 120 for more information. 4.5.1 block error counters the iec-q provides internal counters for far-end and near-end block errors. this allows a comfortable surveillance of the transmission quality at the u-interface. one block error thus indicates that one u-superframe has not been transmitted correctly. no conclusion about the number of bit errors is therefore possible. 4.5.1.1 nebe counter each detected nebe will cause the nebe counter to be incremented. the maximum count is ff h . no further incrementation will be done after maximum count is reached. read out and reset issuing the mon-8 command rben will cause the iec-q to respond with the mon-8 indication abec consisting of the nebe counter value in the second byte of the two byte monitor channel indication. for more information about mon-8 codes, refer to "mon-8 codes", page 228. c0 c7: 8-bit counter value each read operation resets the nebe counter to 00 h . the counter is also reset in all except the following states: mon-8 rben read block errors near-end 10000000 11111011 mon-8 abec answer block error counter 1 0 0 0 0 0 0 0 c7 c6 c5 c4 c3 c2 c1 c0 peb 2091 pef 2091 operational description semiconductor group 179 data sheet 01.99 4.5.1.2 febe counter each detected febe will cause the febe counter to be incremented. the maximum count is ff h . no further incrementation will be done after maximum count is reached. read out and reset issuing the mon-8 command rbef will cause the iec-q to respond with the mon-8 indication aben consisting of the nebe counter value in the second byte of the two byte monitor channel indication. for more information about mon-8 codes, refer to "mon-8 codes", page 228. c0 c7: 8-bit counter value each read operation resets the febe counter to 00 h . the counter is also reset in all except the following states: lt modes nt modes line active synchronized pend. transparent wait for act transparent transparent s/t deactivated error s/t mon-8 rbef read block errors near-end 10000000 11111010 mon-8 abec answer block error counter 1 0 0 0 0 0 0 0 c7c6c5c4c3c2c1c0 lt modes nt modes line active synchronized pend. transparent wait for act transparent transparent s/t deactivated error s/t peb 2091 pef 2091 operational description semiconductor group 180 data sheet 01.99 4.5.1.3 testing block error counters the block error counter is tested by simulating transmission errors on the line. to simulate transmission errors artificially corrupted crc bits (as a matter of fact, inverted crc bits) are send from the lt to the nt side and vice versa. the device detecting corrupted crc bits will start incrementing the corresponding block error counter which can in turn be read out by a mon-8 command, as described above in this chapter. figure 78, page 183, gives a complete overview of the test procedures. describing the commands needed to perform these tests and the corresponding device behavior is the scope of this section. mon-8 ccrc causes the iec-q to permanently transmit inverted crcs. this command may be used on lt side with the lt in transparent or auto mode. on the terminal side ccrc is only required when the device is operated in transparent mode. in nt-auto activation mode corrupted crcs can be requested directly by the lt side with the eoc command rcc. again the crc will be permanently inverted. with the mon-8 command sfb it is possible on lt and nt side to invert single febe-bits. because this command does not provoke permanent febe-bit inversion but sets only one febe-bit to (0) per sfb command, it is possible to predict the exact febe-counter reading. for more information about mon-8 codes, refer to "mon-8 codes", page 228. note 51: the main application for setting single febe-bits are repeater stations not operating in the lt-rp- or nt-rp mode). request corrupt crcs (rcc) if the eoc auto mode is used on the nt side (see "eoc auto/transparent mode", page 55) this command requests the nt side to transmit corrupted (i.e. inverted) crcs upstream to test the lt nebe-counter. simultaneously the febe-counter and mon-1-messages of the nt are disabled. if the eoc transparent mode is used on the nt side the crc will not be corrupted, the febe-counter is enabled and mon-1 febe-messages will be issued, i.e. the iec-q will not react to this command. this command is a predefined eoc command which can be controlled by the mon-0 message issued on the lt side downstream (see "access to eoc of u-interface", page 110). peb 2091 pef 2091 operational description semiconductor group 181 data sheet 01.99 initialization (lt side) acknowledgment (nt and lt side) notify of corrupt crc (ncc) if the eoc auto mode is used on the nt side (see "eoc auto/transparent mode", page 55) this command requests the nt to disable the nebe-counter and mon-1 nebe indications. in the eoc transparent mode the iec-q will not react to this command. this command is a predefined eoc command which can be controlled by the mon-0 message issued on the lt side downstream (see "access to eoc of u-interface", page 110). initialization (lt side) acknowledgment (nt and lt side) return to normal (rtn) if the eoc auto mode is used on the nt side (see "eoc auto/transparent mode", page 55) this command requests the nt to disable all previously received eoc commands. in the eoc transparent mode the iec-q will not react to this command. this command is a predefined eoc command which can be controlled by the mon-0 message issued on the lt side downstream (see "access to eoc of u-interface", page 110). mon-0 rcc request of corrupt crc 00000001 01010011 mon-0 rcc request of corrupt crc 00000001 01010011 mon-0 ncc notify of corrupt crc 00000001 01010100 mon-0 ncc notify of corrupt crc 00000001 01010100 peb 2091 pef 2091 operational description semiconductor group 182 data sheet 01.99 initialization (lt side) acknowledgment (nt and lt side) corrupt crcs (ccrc) if the eoc transparent mode is used on the nt side, or if one of the lt modes is used (see "eoc auto/transparent mode", page 55) this command requests the iec-q to transmit corrupted (i.e. inverted) crcs. it will be executed immediately. if the eoc auto mode is used on the nt side the iec-q will not react to this command. this command is delivered by the mon-8 message (see also "mon-8 codes", page 228). initialization (nt [transparent only], lt [auto/transparent]) no acknowledgment will be issued. normal (norm) disables all previously sent mon-8 latching commands. the command may be used in auto and transparent mode in lt modes and in transparent mode in nt modes. if the eoc auto mode is used on the nt side the iec-q will not react to this command. initialization (nt [transparent only], lt [auto/transparent]): no acknowledgment will be issued. mon-0 rtn return to normal 00000001 11111111 mon-0 rtn return to normal 00000001 11111111 mon-8 ccrc corrupt crc 10000000 11110000 mon-8 norm normal 10000000 11111111 peb 2091 pef 2091 operational description semiconductor group 183 data sheet 01.99 figure 78 block error counter test itd04226 nt transparent iom r -2 (mon-0) ncc ack -0) (mon -1) (mon nebe error count nebe (mon-0) ack rtn -0) (mon (mon-0) rcc ack -0) (mon (mon -1) febe ccrc -8) (mon (mon-0) rtn ack -0) (mon error count febe nt auto-mode stop error detect free error detect free error detect error stop detect lt u eoc acknowledge start inverse crc bits febe = "0" eoc acknowledge eoc acknowledge start inverse crc bits febe = "0" eoc eoc acknowledge end inverse crc bits : rtn eoc : rcc eoc : rtn eoc : ncc (mon-0) ack ncc -0) (mon (mon-8) ccrc -8) (mon rbef norm -8) (mon (mon-0) rtn ack -0) (mon (mon-0) ack rcc -0) (mon rben -8) (mon (mon-0) rtn error count febe nebe count error -2 r iom crc bits end inverse peb 2091 pef 2091 operational description semiconductor group 184 data sheet 01.99 figure 79 crc violation indications itd04234 dd nt sfr(n) sfr(n+1) lt u g(u) crc 1... crc12 no =? yes sfr(n+1.0625) sfr(n+1.0625) febe = "1" febe = "0" sfr(n+0.0625) nebe error counter (mon-1) nebe (mon-8) du (mon-8) (mon-1) febe febe error counter g(u) sfr(n+1.0625) sfr(n+2) sfr(n+2) febe = "0" febe = "1" dd g(u) febe error counter g(u) =? nebe error counter 4 m d), + b (2 du (mon-8) (mon-8) no yes (2 b + d), m4 12 crc ... 1 crc 12 crc ... 1 crc crc 1... crc12 r iom -2 r iom -2 peb 2091 pef 2091 operational description semiconductor group 185 data sheet 01.99 4.6 chip internal test options the iec-q permits limited access to internal test procedures and internal data. this chapter explains how these tests can be performed. 4.6.1 self-test note 52: this section applies only in the nt, nt-pbx and te modes. this test can be requested by the terminal in order to verify correct performance. the self-test is started with the mon-1-command st. no tests are performed within the iec-q. if the st-message has been received correctly, the device returns the mon-1-message stp (self-test passed) to the terminal. with this function the terminal has a possibility to verify the existence of a layer-1 device. initialization (nt side) acknowledgment (nt side) x: do not care for more information about mon-1 commands and codes, see "mon-1 codes", page 227. 4.6.2 receiver coefficient values some of the internal chip registers can be read via mon-8-messages. of interest to the user are the values of the coefficients for equalizer and echo canceller. this information will however only proof useful if a detailed, theoretical chip knowledge exists. registers are read by sending a two-byte mon-8 message rcoef. the first byte identifies the command as an internal register access, the second addresses the register. the 16-bit register value is returned in two mon-8 messages dcoef of two bytes each. table 31 shows the address range for equalizer (26 coefficients) and echo canceller coefficients (36 coefficients). mon-1 st self test 00010000 0001xxxx mon-1 stp self test pass 00010000 0010xxxx peb 2091 pef 2091 operational description semiconductor group 186 data sheet 01.99 initialization read request mon-8 (1. byte) 1 0 0 0 1 0 0 0 ; select register access (2. byte) a a a a a a a a ; coefficient address for each requested coefficient 16 bit are returned in the following manner mon-8 (1. byte) 1 0 0 0 1 0 0 0 (2. byte) d d d d d d d d ; data bits d0 C d7 1) (3. byte) 1 0 0 0 1 1 0 0 (4. byte) d d d d d d d d ; data bits d8 C d15 1) for more information about mon-8 commands and codes, see "mon-8 codes", page 228. 4.7 test loop-backs test loop-backs are specified by the national ptts in order to facilitate the location of defect systems. four different loop-backs are defined. the position of each loop-back is illustrated in figure 80. 1) binary complement format (ffff h = C1d) table 31 internal coefficient addresses register address range (decimal) 1. filter coefficient echo canceller 6 41 41 equalizer 44 69 69 peb 2091 pef 2091 operational description semiconductor group 187 data sheet 01.99 figure 80 test loop-backs supported by the iec-q loop-backs #1, #1a and #2 are controlled by the exchange. loop-back #3 is controlled by the terminal. all four loop-back types are transparent. this means all bits that are looped back will also be passed onwards in the normal manner. the next sections describe how these loop-backs are closed and opened using the c/i- and mon-commands available to the iec-q. 4.7.1 analog loop-back (no. 1/no. 3) both loop-back #1 and loop-back #3 are closed by the iec-q as near to the u-interface as possible. for this reason they are also called analog loop-backs. data transmitted to the u-interface are looped back as well. only this internal loop-back signal is processed; signals received from the u-interface are ignored. because all analog signals will still be passed on to the u-interface the opposite station (nt in case of #1, lt in case of #3) will be activated as well, if available. states because signals received from the metallic line are ignored, the iec-q stays in lt modes in the "line active" state for loops no.1 and no.1a (upstream act-bit cannot be received, see "lt modes state diagram", page 147). in lt-rp mode the device stays in the "transparent" state (see "state machine in repeater modes", page 173). in nt modes (no.3) the device stays in "analog loop-back" (see "nt modes state diagram", page 161). itd04218 loop 2 2 loop s-bus iom r sbcx iec-q nt iec-q icc r iom loop 2 3 loop icc iec-q pbx or te iec-q iec-q r iom 1a loop uu repeater (optional) loop 1 iec-q iom r exchange peb 2091 pef 2091 operational description semiconductor group 188 data sheet 01.99 analog loop-back control before an analog loop-back is closed with the c/i-command arl (activation request loop-back, see "c/i channel codes", page 224), the device should have been reset. in order to open an analog loop-back correctly, reset the device into the test state with the c/i-command res (or by pin reset). this ensures that the echo coefficients and equalizer coefficients will converge correctly when activating the following time. although loop-back #1 and loop-back #3 are closed with the same command and perform the same function, they cannot be started from the same state: loop-back #1 is closed when in the state "deactivated" (lt side); loop-back #3 can only be closed in the state "test" (nt side). for examples of programming these loops, refer to "examples for analog loop-back control", page 236. 4.7.2 partial and complete loop-back (no. 2) for loop-back #2 several alternatives exist. both the type of loop-back and the location may vary. three loop-back types belong to the loop-back-#2 category: C complete loop-back C b1-channel loop-back C b2-channel loop-back the complete loop-back comprises both b-channels and the d-channel. it may be closed either in the iec-q itself or in a downstream device. single-channel loop-backs are always performed within the iec-q. in this case the digital data of dout will be directly fed back into din. this also applies if the complete loop-back is closed in the iec-q. normally loop-back #2 is controlled from the exchange. the eoc commands lbbd, lb1 and lb2 are used. they will be recognized and executed automatically in the nt iec-q if the eoc auto mode is selected (see "eoc auto/transparent mode", page 55). due to the automatic acknowledgment in eoc auto mode, the eoc-message will be mirrored back immediately by the nt as a confirmation 1) . eoc commands are accessed via mon-0 messages. for more details, see "access to eoc of u-interface", page 110. if the eoc transparent mode is used in the nt the mon-8-commands lbbd, lb1 and lb2 are available (see "eoc auto/transparent mode", page 55). all loop-back functions are latched. this allows channel b1 and channel b2 to be looped back simultaneously. all loop-backs are opened when the eoc command rtn or the mon-8 command norm is sent. a detailed operational description will be give in the subsequent sections. 1) note however that this confirmation is issued before the loop-back function is initialized. therefore it cannot be regarded as an acknowledgment that the loop-back function was started correctly peb 2091 pef 2091 operational description semiconductor group 189 data sheet 01.99 4.7.2.1 complete loop-back when receiving the eoc-command lbbd in auto mode, the nt iec-q does not close the loop-back immediately. because the intention of this loop-back is to test the complete nt, the iec-q passes the complete loop-back request on to the next downstream device. this is achieved by issuing the c/i-code ail in the "transparent" state or c/i = arl in states different than "transparent" (see "state machine in nt modes", page 160). if the downstream device is not able to close the complete loop-back, a mon-8-message lbbd may be returned to the nt iec-q. this then will close the complete loop-back within the iec-q itself (b1 + b2 + d-channels). all remaining iom ? -2-information (monitor, c/i-channel as well as the bits mr and mx) are still read from the iom ? -2 or the p interface (if used). for this reason it is still possible for a layer-2 device to deactivate the nt despite the fact that the loop-backs are controlled by the exchange. note 53: if operated in eoc auto mode, the complete loop-back can only be closed in the iec-q if previously the eoc-command lbbd was received. without this eoc-message the mon-8-command lbbd will be ignored. if operated in eoc transparent mode, a complete loop-back may be closed at any time with mon-8 lbbd. in eoc auto mode the complete loop-back is reset after rtn has been received in the eoc-channel. in the eoc transparent mode mon-8 norm is used for this purpose. no reset as for loop-backs #1 or #3 is required for loop-back #2. the line is active and ready for data transmission. as an example figure 81 illustrates these two options if the iec-q is used together with the sbc-x and the icc. figure 81 complete loop-back options in nt modes itd04219 iec-q auto-mode 2b+d 2b+d sbcx icc mon-8 "lbbd" eoc "lbbd" = u c/i = ail/arl peb 2091 pef 2091 operational description semiconductor group 190 data sheet 01.99 4.7.2.2 single-channel loop-backs single-channel loop-backs are always performed directly in the iec-q. no difference between the b1-channel and the b2-channel loop-back control procedure exists. they are therefore discussed together. in eoc auto mode the b1-channel is closed with the eoc-command lb1. lb2 causes the channel b2 to be looped back. because these functions are latched, both channels may be looped back simultaneously by sending first the command to close one channel followed by the command for the second one. in the eoc transparent mode, single channels are closed with the corresponding mon-8-commands. single-channel loop-backs are resolved in the same manner as described for the complete loop-back. the nt may be deactivated with layer 2 while single loop-backs are closed. 4.7.2.3 repeater loop-back (no. 1a) loop-back #1a is always closed in the repeater. functionally it corresponds to loop-backs #1 and #3 on the exchange and on the network side. if a line contains more than one repeater unit, it is possible to address each unit individually in order to close loop-back #1a in the specified unit only. for loop-back #1a everything described in section "analog loop-back (no. 1/no. 3)", page 187 applies: the loop-back is opened with the c/i-command res, closed with the c/i-command arl, and it is closed as near to the u-interface as possible. the difference results from the fact that the command arl needs to be generated by the repeater control unit (p or asic) according to national repeater specifications. this specification defines an eoc-command which will activate loop-back #1a if received in conjunction with the repeater address (001 b ). the nt-rp is operating in transparent mode. the repeater control unit watches for mon-0-commands with address (001 b ). if the predefined loop-back #1a command is received, the repeater control unit sends the c/i-code arl to the lt-rp and loop-back #1a will be closed. for more information, see "eoc addressing management", page 257. figure 82 illustrates this in a system with two repeater units where the second unit is requested to close loop-back #1a. peb 2091 pef 2091 operational description semiconductor group 191 data sheet 01.99 figure 82 closing loop-back #1a in a multi-repeater system 4.7.2.4 codes this section gives the monitor channel messages used to control test loop-back #2. for more information about monitor messages and codes in general, see also "monitor channel codes", page 226. codes used in eoc auto modes for partial loop-backs initialization from lt acknowledgment (issued on lt and nt side) initialization from lt acknowledgment (issued on lt and nt side) mon-0 lb1 close loop-back in b1-channel 00000001 01010001 mon-0 lb1 close loop-back in b1-channel 00000001 01010001 mon-0 lb2 close loop-back in b2-channel 00000001 01010010 mon-0 lb2 close loop-back in b2-channel 00000001 01010010 itd04220 nt lt rp nt rp m p ~ ~ uu ~ ~ 1 repeater p m rp nt rp lt u ~ ~ lt adr = 1 2 = adr adr = 0 0 = adr 0 = adr eoc adr = 2 no. no. repeater 2 c/i = ail # arl = c/i ( m p) 2 #1a eoc command = lbbd peb 2091 pef 2091 operational description semiconductor group 192 data sheet 01.99 codes used in eoc auto modes for complete loop-backs if the complete loop should be closed outside the iec-q, the following code is applied. initialization (lt side) acknowledgment (issued on lt and nt side) if the complete loop should be closed inside the iec-q, the following code is applied. initialization (lt side) acknowledgment (issued on lt and nt side) close loop in iec-q (nt side) codes used in eoc transparent modes for partial loop-backs single-channel and complete loop-backs are closed from the nt side with the mon-8-commands. mon-0 lbbd close loop-back 2b + d 00000001 01010000 mon-0 lbbd close loop-back 2b + d 00000001 01010000 mon-0 lbbd close loop-back 2b + d 00000001 01010000 mon-0 lbbd close loop-back 2b + d 00000001 01010000 mon-8 lbbd close loop-back 2b + d 10000000 11110001 peb 2091 pef 2091 operational description semiconductor group 193 data sheet 01.99 initialization (nt side) no acknowledgment issued. initialization (nt side) no acknowledgment issued. initialization (nt side) no acknowledgment issued. 4.8 chip identification the chip identification of iec-q version 5.3 is "03 h ". it is the same chip identification as versions 5.1 and 5.2. if the mon-8 command rid is issued the iec-q will respond by indicating this identification via the mon-8 command aid (see also "mon-8 codes", page 228). codes identification demand response mon-8 lb1 close loop-back in b1-channel 10000000 11110100 mon-8 lb2 close loop-back in b2-channel 10000000 11110010 mon-8 lbbd close loop-back in 2b + d 10000000 11110001 mon-8 rid read identification 10000000 010 CCCa0a1 mon-8 aid answer identification 10000000 00000011 peb 2091 pef 2091 operational description semiconductor group 194 data sheet 01.99 4.9 access to power status pins this chapter deals with the operational aspects of accessing the power controller maintenance features provided by the iec-q. pins ps1 and ps2 are available to support these features. furthermore, in stand-alone mode pin diss is also available. 4.9.1 monitoring primary and secondary nt power supply note 54: this section applies only in nt and te modes. power status bits 1 and 2 (ps1/2) are used to monitor both primary and secondary nt power supply. this information is transferred via the single bits channel to the exchange side. for information about the single bits, see "single bits channel", page 69. ps1 the primary power supply status bit (bit m42 of the u-frame) is level sensitive. with pin ps1 set to (1) the overhead bit is set to (1). with pin ps1 set to (0) overhead bit m42 is set to (0). ps2 the secondary power supply status bit (bit m43 of the u-frame) is level sensitive. with pin ps2 set to (1) the overhead bit is set to (1). with pin ps2 set to (0) overhead bit m43 is set to (0). 4.9.2 monitoring remote power feed circuit in lt modes note 55: this section applies only in lt modes. the first power status pin ps1 is used to monitor the remote power feed circuit of the subscriber line. a high level 1 indicates that the remote power has been turned off. in order to indicate this to the processing unit, the c/i-code "hi" (0011 b ) will be issued and the device is reset into the "test" state. an existing communication link will break down. 4.9.3 monitoring power feed current in lt modes note 56: this section applies only in lt modes. the pin ps2 provides a serial interface in order to read in the value of the current fed to the subscriber line by the power controller. this feature is available only in combination with a power controller which supports this feature (the iepc does not). the power controller is to send eight-bit data which are read synchronous to the iom ? -2-clock signals. timing of the serial data stream forwarded to pin ps2 must be synchronous to the signals of pin din (see figure 83 for details). peb 2091 pef 2091 operational description semiconductor group 195 data sheet 01.99 figure 83 serial data port of pin ps2 in lt modes this value can be read out through mon8-channel. the mon-8 command rpfc (read power feed current) requests the iec-q to return the current feed value which has been read from pin ps2. the iec-q will then respond by issuing the mon-8 indication "apfc" (answer power feed current) in the next iom ? -2 frame available. the codes of these commands are given below. refer to "iom ? -2 monitor channel", page 76 1) for informations about the structure and function of the monitor channel. see also "mon-8 codes", page 228, for a summary of all available mon-8 command. 4.9.4 access to pin diss note 57: this section applies only in stand-alone mode. nt and te modes note 58: this feature is only available in eoc auto mode (see "eoc auto/transparent mode", page 55). in these modes the output pin diss (disable) is set to (1) if the eoc-command "close complete loop" (lbbd) has been detected by the nt (see "predefined eoc codes", page 231). it may be used to test a secondary power source (e.g. battery check). the diss-pin is set back to (0) with the eoc-command "rtn" or a reset. 1) if the microprocessor mode is being used refer to "monitor channel access", page 101 mon-8 rpfc read power feed current 10000000 11111000 mon-8 apfc answer power feed current 1 0 0 0 0 0 0 0 d7d6d5d4d3d2d1d0 itd04240 b1 channel 0 1 channel 1 b b1 channel x 1 b pfc pfc fsc ps 2 din peb 2091 pef 2091 operational description semiconductor group 196 data sheet 01.99 lt modes the pin diss is used for switching off the remote power supply of the subscriber line. it is set to 1 by the c/i-command "ltd" (0011 b ). a software reset with c/i = "res" does not affect the diss-pin. while the diss-pin is set to (1), the device is in the "test" state "state machine in lt modes", page 146. 4.10 access to power controller interface note 59: this chapter applies only in stand-alone mode. the interface consists of three data bits pcd0 ... 2, two address bits pca0,1, read and write signals pcrd and pcwr respectively as well as an interrupt facility int. for dynamical characteristics, see "power controller interface timing", page 277. for an example for programming code, see "example for programming power controller interface", page 235. 4.10.1 data port communication with the data port (pcd0 ... 2, pca0,1, pcrd and pcwr ) of the power controller interface is established with local monitor messages (mon-8) of the iom ? -2 interface. table 32 lists all mon-8 commands that are relevant to the power controller interface. the codes of these commands are given below. for more information about programming mon-8 commands see "mon-8 codes", page 228 table 32 mon-8 and c/i-commands channel code function mon-8 wci write to interface. address and data is contained in the mon-command. the address is latched, data is not latched. mon-8 rci read from interface at specified address. address is latched and the current value of the data port is read. the result is returned to the user with mon-8 "aci". mon-8 aci answer from interface. after a rci-request the value of three data bits at the specified address is returned. peb 2091 pef 2091 operational description semiconductor group 197 data sheet 01.99 . after the receipt of a mon-8-command the iec-q will set the address/data bits and generate a read or write pulse. the address bits are latched, and the output is stable until a new dedicated mon-8 command is issued. the initial value on the address lines after a software, hardware or power-on reset is (11 b ). 4.10.2 interrupt for every change at the input pin int, the iec-q will transmit a c/i-channel code (0110 b ), int, in 4 successive iom ? -2-frames. note 60: interpretation of the interrupt cause and resulting actions need to be performed by the control unit. the input condition of the pin int is sampled every 4 iom ? -2-frames. an interrupt indication must therefore be applied to pin "int" for at least 4 iom ? -2-frames. mon-8 wci write controller interface 10000000 011d0d1d2a0a1 mon-8 rci read controller interface 10000000 010 CCCa0a1 mon-8 aci answer controller interface 10000000 d0d1d2CCCCC peb 2091 pef 2091 operational description semiconductor group 198 data sheet 01.99 figure 84 sampling of interrupts 4.11 s/g bit and bac bit operations note 61: this chapter applies only in the p-te mode (see "setting operating modes", page 50). if dcl = 1.536 mhz the iom ? -2 interface consists of three iom ? -2 channels (see "terminal timing mode", page 73). the last octet of an iom ? -2 frame includes the s/g and the bac bit. the s/g bit is always written and never read by the iec-q. its value depends on the last received eoc-command and on the status of the bac bit. the processing mode for the s/g bit is selected via bits swst:bs, swst:sgl and adf:cbac (see "adf-register", page 219). the following table and state machine give the detailed behavior of the complete s/g bit control function. itd10294 125 m s 1ms ms 0.5 c/i code int int c/i code int int example a example b r iom -2 frames peb 2091 pef 2091 operational description semiconductor group 199 data sheet 01.99 table 33 s/g bit control overview swst: bs swst: sgl adf: cbac description application 00x 1) 1) x is dont care s/g bit always "0" (default) 0 1 0 s/g bit always "1" s/g and bac are handled by other devices than the iec-q 0 1 1 s/g bit set to "1" continuously with eoc 25 h received, reset to "0" with eoc 27 h received bac bit controls s/g-bit, upstream d-channel not affected elic ? on linecard, interframe fill of terminals contains zeroes (e.g. 01111110) 1 0 0 s/g bit set to "1" for 4 iom ? -2-frames with eoc 25 h received, automatically reset to "0" after that. this is the default setting of adf:cbac after reset synchronization of base station, e.g. ibmc or mbmc 1 0 1 s/g bit set to "0" for 4 iom ? -2-frames with eoc 25 h received, automatically reset to "1" after that synchronization of base station, e.g. ibmc or mbmc. inverse polarity to the setting 1,0,0 (last row) 1 1 0 s/g bit set to "1" continuously with eoc 25 h received, reset to "0" with eoc 27 h received bac bit not read by iec-q v 5.3 1 1 1 s/g bit set to "1" continuously with eoc 25 h received, reset to "0" with eoc 27 h received bac bit controls upstream d-channel and s/g-bit elic ? on linecard, interframe fill of terminals are ones peb 2091 pef 2091 operational description semiconductor group 200 data sheet 01.99 4.11.1 state machine the exact s/g bit control function is given in the following state diagrams. the values in the state diagrams are to be interpreted as follows : figure 85 state machine notation for s/g bit control state n am e o utput value state n um ber input value input value peb 2091 pef 2091 operational description semiconductor group 201 data sheet 01.99 figure 86 state machine for s/g bit control (part 1) bs=1 and sgl=0 and cbac=0 t4 expired eoc=25, t4 set bs=1 and sgl=0 and cbac=1 eoc=27 eoc=25 (bs=sgl=1) and cbac=0 eoc=25 eoc=27 1 reset d0=0;sg=1 3 sg to 1 d0=0;sg=1 pmode=0 or act=1 or te=0 (pmode=act=te=1) and (bs=cbac=0) and (sgl=1) (pmode=act=te=1) and (bs=sgl=0) 2 sg to 0 d0=0;sg=0 1 4a sg-4t to 0 d0=0;sg=0 5a sg-4t to 1 d0=0;sg=1 t4 expired eoc=25, t4 set 4b sg-4t to 1 d0=0;sg=1 5b sg-4t to 0 d0=0;sg=0 1 6 s/g transp. d0=0;sg=x** ) 7 s/g transp. 1 d0=0;sg=1 8 s/g transp. 0 d0=0;sg=0 * ) * ) * ) * ) unconditional transition if input combination is met ** ) x = undefined peb 2091 pef 2091 operational description semiconductor group 202 data sheet 01.99 figure 87 state machine for s/g bit control (part 2) hdlc ctrl d0=0;sg=1 8 bac-edge d0=0;sg=1 9 bac=0 td1 set wait for eoc d0=0;sg=1 10 td1 expired s/g go d0=0;sg=0 12 s/g stop d0=0;sg=1 13 eoc=27 eoc=25 (pmode=act=te=1) and (sgl=cbac=1) and (bs=0) and (bac=1) eoc=27 eoc=25 * ) * ) unconditional transition if input combination is met peb 2091 pef 2091 operational description semiconductor group 203 data sheet 01.99 figure 88 state machine for s/g bit control (part 3) hdlc ctrl d0=0;sg=1 14 bac-edge d0=1;sg=1 15 wait for eoc d0=1;sg=1 17 s/g go d0=1;sg=0 18 s/g stop d=1;sg=1 19 hdlc-f go d0=0;sg=0 20 hdlc-f stop d0=0;sg=1 21 (pmode=act=te=1) and (bs=sgl=cbac=1) and (bac=1) bac=0 td1 set td1 expired eoc=27 eoc=25 eoc=27 eoc=25 hdlc_frame hdlc_frame eoc=25 eoc=27 * ) * ) unconditional transition if input combination is met peb 2091 pef 2091 operational description semiconductor group 204 data sheet 01.99 i table 34 state machine input signals for s/g control no. signal name description 1 pmode corresponds to the pmode pin. set to "1" (only) in the microprocessor mode 2 te this input is set to "1" (only) in the te mode 3 act "1" on this input indicates receive synchronization (e.g. in the transparent state, see users manual 02.95 of the peb 2091-version 4.3, page 175). 4 bs swst:bs bit. 5 sgl swst:sgl bit. 6 cbac adf:cbac bit. 7 eoc=25 this input indicates that the eoc code 25h (stop) was received from the u-interface. 8 eoc=27 this input indicates that the eoc code 27h (go) was received from the u-interface. 9 t1 set an internal 500 micro seconds timer is enabled. 10 t1 expired the 500 micro seconds timer (see 9) has expired. 11 td1 set an internal timer td1 is enabled. the length of this timer depends on the position of the eoc frame in the currently received u data. it varies between 7.5 and 15 ms. 12 td1 expired the timer td1 has expired, (see 11). 13 bac bac bit on din. this is bit no. 27 positioned in the third iom ? -2 slot table 35 state machine output signals for s/g control no. signal name description 1 sg value of the s/g bit on dout. the s/g bit is bit no. 27 in the third slot on dout. 2 d0 sets the d channel upstream to "0" if active ("1") peb 2091 pef 2091 operational description semiconductor group 205 data sheet 01.99 4.11.2 indication of s/g bit status on pin sg note 62: this feature is only available if one of the packages t-qfp-64 or m-qfp-64 is being used. this function is not available in the p-lcc-44 package. the s/g bit status information will be additionally provided on pin sg (see "miscellaneous function pins", page 46). figure 89 s/g bit status on pin s/g note that in state number 6 of the s/g bit control state machine (see figure 86, page 201) the s/g bit is not defined. in this case the polarity of pin sg may differ from the polarity of the s/g bit on iom ? -2. for timing properties see "timing properties of pin sg in te mode", page 286. 0 10 s/g s/g s/g iom ? -2 frame downstream sg pin peb 2091 pef 2091 register description semiconductor group 206 data sheet 01.99 5 register description note 63: this chapter applies only in p mode. the setting of the iec-q in p mode and the transfer of data are programmed with registers. the address map and a register summary are given in table 36 and in table 37, respectively. peb 2091 pef 2091 register description semiconductor group 207 data sheet 01.99 table 36 register overview reg name access address (hex) reset value comment page no. ista read 0 00 h interrupt status register 210 mask write 0 ff h interrupt mask register 211 stcr write 1 04 h status control register 212 mor read 2 ff h read monitor data 222 mox write 2 ff h write monitor data 222 dru read 3 ff h read d from u 221 dwu write 3 ff h write d to u 221 adf2 write 4 18 h additional features reg. 2 214 read 5 reserved for the test mode (must not be used in normal operation) write 5 rb1u read 6 00 h read b1 from u 221 wb1u write 6 00 h write b1 to u 221 rb2u read 7 00 h read b2 from u 221 wb2u write 7 00 h write b2 to u 221 rb1i read 8 00 h read b1 from iom ? -2 221 wb1i write 8 00 h write b1 to iom ? -2 221 rb2i read 9 00 h read b2 from iom ? -2 221 wb2i write 9 00 h write b2 to iom ? -2 221 mosr read a 00 h monitor status register 215 mocr write a 00 h monitor control register 216 dri read b ff h read d from iom ? -2 221 dwi write b ff h write d to iom ? -2 221 ciru read c 03 h read c/i-code from u 217 ciwu write c c3 h write c/i-code to u 217 ciri read d 03 h read c/i-code from iom ? -2 218 ciwi write d c7 h write c/i-code to iom ? -2 218 adf write e 14 h additional features reg. 219 swst write f 00 h switch status register 220 peb 2091 pef 2091 register description semiconductor group 208 data sheet 01.99 table 37 register summary add- ress 76543210name 0 h d cici cicu sf mdr b1 b2 mda ista r 0 h d cici cicu sf mdr b1 b2 mda mask w 1 h test1 test2 ms2 ms1 ms0 tm1 tm2 auto stcr w 2 h mor r 2 h mox w 3 h dru r 3 h dwu w 4 h te1 mto dod sfen min 1 icec 1 adf2 w 6 h rb1u r 6 h wb1u w 7 h rb2u r 7 h wb2u w 8 h rb1i r 8 h wb1i w 9 h rb2i r 9 h wb2i w a h mdr mer mda mab mac mosr r a h mre mrc mxe mxc 1 1 1 1 mocr w b h dri r b h dwi w c h 0 0 c/i c/i c/i c/i ciru r c h spu 1 c/i c/i c/i c/i 1 1 ciwu w d h c/i c/i c/i c/i c/i c/i ciri r d h c/i c/i c/i c/i c/i c/i 1 1 ciwi w e h wtc2 wtc1 pcl1 pcl0 1 uvd bcl cbac adf w f h wt b1 b2 d ci mon bs sgl swst w peb 2091 pef 2091 register description semiconductor group 209 data sheet 01.99 5.1 interrupt structure the cause of an interrupt is determined by reading the interrupt status register (ista). in this register, 7 interrupt sources can be directly read. interrupt bits are cleared by reading the corresponding registers. ista:d is cleared after dri and dru have been read. ista:b1 is cleared after rb1i and rb1u have been read. ista:b2 is cleared after rb2i and rb2u have been read etc. ista:cici is cleared after ciri is read, ista:cicu is cleared after ciru is read. ista:sf indicates a superframe marker received from the transceiver core. it is cleared when the ista register has been read. pin int is set to "0" if one bit of ista changes from "0" to "1", except for the bit masked in the mask register. the mask register allows to prevent an interrupt to influence the int pin. setting the bits of mask that correspond to the bits of ista to "1" masks the bits, i.e. the bits are still set in ista, but they do not contribute to the input of the nor-function on the interrupt bits which sets the int pin. the interrupt structure is illustrated in figure 90: figure 90 interrupt structure 5.1.1 monitor-channel interrupt logic the monitor data receive (mdr) and the monitor end of reception (mer) interrupt status bits have two enable bits, monitor receive interrupt enable (mre) and mr-bit control (mrc). the monitor channel data acknowledged (mda) and monitor channel data abort (mab) interrupt status bits have a common enable bit monitor interrupt enable (mxe). mre prevents the occurrence of the mdr status, including when the first byte of a packet is received. when mre is active ("1") but mrc is inactive, the mdr interrupt status is generated only for the first byte of a receive packet. when both mre and mrc are active, mdr is generated and all received monitor bytes - marked by a low edge in itd08114 d cici cicu sf mdr b1 b2 mda int mask ista mda b2 b1 mdr sf cicu cici d mdr mda mosr mer mab mac mocr mxc mrc mxe mre peb 2091 pef 2091 register description semiconductor group 210 data sheet 01.99 mx bit - are stored. additionally, an active mrc enables the control of the mr handshake bit according to the monitor channel protocol. 5.2 detailed register description 5.2.1 ista-register read address 0 h the i nterrupt sta tus register (ista) generates an interrupt for the selected channel. interrupt bits are cleared by reading the corresponding register. reset value: 00 h 76543210 d cici cicu sf mdr b1 b2 mda d d-channel interrupt 1= indicates an interrupt that 8 bits d-channel data have been updated 0= occurs after dri and dru have been read cici c/i-channel interrupt iom ? -2 1= indicates a change in the c/i-channel on iom ? -2 0= occurs after ciri is read cicu c/i-channel interrupt u 1= indicates a change in the c/i-channel coming from the transceiver core 0= occurs after ciru is read sf superframe marker 1= indicates a superframe marker received from the transceiver core 0= occurs when the ista-register has been read mdr monitor data receive interrupt 1= indicates an interrupt after the mosr:mdr or the mosr:mer bits have been activated 0= indicates the inactive interrupt status b1 b1-channel interrupt 1= indicates an interrupt every time b1-channel bytes arrive 0= occurs after rb1i and rb1u have been read peb 2091 pef 2091 register description semiconductor group 211 data sheet 01.99 b2 b2-channel interrupt 1= indicates an interrupt every time b2-channel bytes arrive 0= occurs after rb2i and rb2u have been read mda monitor data transmit interrupt 1= indicates an interrupt after the mosr:mda or the mosr:mab bits have been activated 0= indicates the inactive interrupt status 5.2.2 mask-register write address 0 h the interrupt mask register (mask) can selectively mask each interrupt source in the ista register by setting to "1" the corresponding bit. reset value: ff h 76543210 d cici cicu sf mdr b1 b2 mda d d-channel mask 1= prevents an interrupt ista:d to influence the int pin 0= disables the function described above cici cici-channel mask iom ? -2 1= prevents an interrupt ista:cici to influence the int pin 0= disables the function described above cicu cicu-channel mask u 1= prevents an interrupt ista:cicu to influence the int pin 0= disables the function described above sf superframe marker mask 1= prevents an interrupt ista:sf to influence the int pin 0= disables the function described above peb 2091 pef 2091 register description semiconductor group 212 data sheet 01.99 mdr monitor data receive mask 1= prevents an interrupt ista:mdr to influence the int pin 0= disables the function described above b1 b1-channel mask 1= prevents an interrupt ista:b1 to influence the int pin 0= disables the function described above b2 b2-channel mask 1= prevents an interrupt ista:b2 to influence the int pin 0= disables the function described above mda monitor data transmit mask 1= prevents an interrupt ista:mda to influence the int pin 0= disables the function described above 5.2.3 stcr-register write address 1 h the st atus c ontrol r egister (stcr) selects the operating modes of the iec-q as given in table 2, " setting modes of operation (stand-alone and p mode)", on page 51. note 64: the stcr-register is only reset after a power-on. please refer also to "reset behavior", page 94. reset value: 04 h 7 6543210 burst lt ts2 ts1 ts0 tm1 tm2 auto burst selection of burst modes 1= selects the burst modes (lt, nt-pbx) 0= selects the non-burst modes (nt, te, cot-512/1536, lt/nt-rp) lt selection of lt modes 1= selects the lt modes (lt,cot-512/1536, lt-rp) 0= selects the non lt modes (nt, te, nt-pbx, nt-rp) peb 2091 pef 2091 register description semiconductor group 213 data sheet 01.99 ts2 mode selection 2 selects operation mode according to table 2, page 51 ts1 mode selection 1 selects operation mode according to table 2, page 51 ts0 mode selection 0 selects operation mode according to table 2, page 51 tm1 test-mode-bit 1 this bit determines, in combination with stcr:tm2, the operation modes. see table below tm2 test-mode-bit 2 this bit determines, in combination with stcr:tm1, the operation modes. see table below auto selection between eoc auto and transparent mode 1= sets the auto mode for eoc channel processing 0= sets the transparent mode for eoc channel processing test-mode tm1 tm2 normal mode 1 0 send single-pulses 1 1 data-through 0 1 peb 2091 pef 2091 register description semiconductor group 214 data sheet 01.99 5.2.4 adf2-register write address 4 h ad ditional f eatures register 2 (adf2).write address 4 h . reset value: 18h 76543210 te1 mto dod sfen min 1 icec 1 te1 terminal equipment channel 1 1= enables the iec-q to write monitor data on dout to the mon1 channel instead of the mon0 channel and to write 6-bit c/i indications on dout into the c/i-channel 1 0= enables the normal operations where the iec-q addresses only iom ? -2 channel 0 mto monitor procedure time-out 1= disables the internal 6ms monitor time-out 0= enables the internal 6ms monitor time-out dod dout open drain 1= selects pin dout to be open drain 0= selects pin dout to be tristate sfen superframe enable 1= enables the superframe marker function 0= disables the superframe marker function min monitor-in-bit 1= combined with the swst:mon = "1" and adf2:te1 = "0" bits, enables the controller to access the core of the iec-q 0= combined with the swst:mon = "1" and adf2:te1 = "0" bits, enables the controller to access the iom ? -2 interface directed out of the iec-q icec iom ? -2 clocks enable control 1= inverts meaning of pin ice. clocks are enabled if pin ice=0. clocks are disabled if pin ice=1 0= the status of pin ice is valid (reset value) peb 2091 pef 2091 register description semiconductor group 215 data sheet 01.99 5.2.5 mosr-register read address a h the mo nitor s tatus r egister (mosr) indicates the status of the monitor channel. reset value: 00 h 76543210 mdr mer mda mab mac mdr monitor channel data received interrupt 1= generates an interrupt status after the receiving device has stored the contents of the mox register in the mor register 0= inactive interrupt status mer monitor channel end of reception interrupt 1= is generated after two consecutive inactive mx bits (end of message) or as a result of a handshake procedure error 0= indicates that the transmission is running mda monitor channel data acknowledged 1= results after a monitor byte is acknowledged by the receiving device 0= occurs when the receiver waits for an acknowledge of the monitor bit mab monitor channel data abort 1= indicates that during a transmission the receiver aborted the process by sending an inactive ("1") mr bit value in two consecutive frames 0= indicates that the transmission is running properly and that no abort request has been activated mac monitor channel active 1= indicates a transmission on the monitor channel 0= indicates that the transmitter is inactive, i.e. ready for a transmission peb 2091 pef 2091 register description semiconductor group 216 data sheet 01.99 5.2.6 mocr-register write address a h the mo nitor c ontrol r egister (mocr) allows to program and control the monitor channel as described in the section 5.1.1. reset value: 00 h 76543210 mre mrc mxe mxc 1 1 1 1 mre monitor receive interrupt enable 1= enables the monitor data receive (mdr) interrupt status bit; mre = 1 enables the monitor data receive (mdr) and the monitor end of reception (mer) interrupt status bits 0= masks the mdr and the mer bits mrc monitor channel receive control 1= enables the control of the mr bit internally by the iec-q according to the monitor channel protocol 0= enforces a "1" (inactive state) in the monitor channel receive (mr) bit mxe monitor transmit interrupt enable 1= combined with the mxc bit tied to "1" enable the monitor channel data acknowledged (mda) and the monitor channel data abort (mab) interrupt status bits 0= masks the mda and the mab bits mxc monitor channel transmit control 1= enables the control of the mx bit internally by the iec-q according to the monitor channel protocol 0= enforces a "1" (inactive state) in the monitor channel transmit (mx) bit peb 2091 pef 2091 register description semiconductor group 217 data sheet 01.99 5.2.7 ciru-register read address c h the r ead c/i -code from u register (ciru) reads the c/i-code from the transceiver core. reset value: 03 h 76543210 c/i c/i c/i c/i 7., 6. bits set to "0". 5.-2. bits contain the c/i-indication coming from the transceiver core. 1., 0. bits set to "1". 5.2.8 ciwu-register write address c h the w rite c/i -code to u register (ciwu) writes the c/i-code to the transceiver core. reset value: c3 h 76543210 spu 1 c/i c/i c/i c/i 1 1 spu software power-up bit valid only in the nt mode. 1= data on din will be transparently transmitted to the transceiver core (default) 0= data on din will be ignored and binary "0" will be continuously transmitted to the transceiver core if the nt mode is selected (pin lt="0") 6. bits set to "1" 5.-2. bits contain the c/i-code going to the transceiver core 1., 0. bits set to "1" peb 2091 pef 2091 register description semiconductor group 218 data sheet 01.99 5.2.9 ciri-register read address d h the r ead c/i -code from iom ? -2 register (ciri) reads the c/i-code from the iom ? -2 interface. reset value: 03 h 76543210 c/i c/i c/i c/i c/i c/i 7., 6. bits adf2:te1 = 1 indicates that the c/i-channel 1 in the te mode can be accessed and that the c/i-channel on iom ? -2-channel 0 is passed transparently from the transceiver core to the iom ? -2. the two bits contain c/i-code adf2:te1 = 0 sets the normal mode. the two bits are set to "0" 5.-2. bits contain the c/i-command coming from the iom ? -2 1., 0. bits set to "1" 5.2.10 ciwi-register write address d h the w rite c/i -code to i om ? -2 register (ciwi) writes the c/i-code to the iom ? -2 interface. reset value: c7 h 76543210 c/i c/i c/i c/i c/i c/i 1 1 7., 6. bits these bits are the msbs of the 6-bit wide c/i code in iom ? -2 channel 1 if adf2:te1 = 1. if adf2:te1 = 0 these two bits have no effect. they should however be set to 1 for future compatibility 5.-2. bits contain the c/i-code going to the iom ? -2 1., 0. bits set to "1" peb 2091 pef 2091 register description semiconductor group 219 data sheet 01.99 5.2.11 adf-register write address e h ad ditional f eatures register (adf). reset value: 14 h 76543210 wtc2 wtc1 pcl1 pcl0 1 uvd bcl cbac wtc2, wtc1 watchdog controller the bit patterns "10" and "01" has to be written in wtc1 and wtc2 by the enabled watchdog timer within 132ms. if it fails to do so, a reset signal of 5ms at pin rst is generated pcl1, pcl0 prescaler the clock frequency on mclk is selected by setting the bits according to the table below: uvd undervoltage detector 1= enables the undervoltage detector. for details see "undervoltage detection", page 92 0= disables the undervoltage detector bcl bit clock 1= changes the dcl-output into the bit-clock mode 0= gives the doubled bit clock on the dcl-output cbac control bac operates in combination with swst:sgl and swst:bs bits to control the s/g bit and the bac bit. for the operational description see "s/g bit and bac bit operations", page 198 pcl1 pcl0 frequency at mclk (mhz) 0 0 7.68 0 i 3.84 i 0 1.92 i i 0.96 peb 2091 pef 2091 register description semiconductor group 220 data sheet 01.99 5.2.12 swst-register write address f h the sw itch st atus register (swst) selects the switching directions of the processor interface (pi). reset value: 00 h 76543210 wt b1 b2 d ci mon bs sgl wt watchdog timer 1= enables the watchdog timer (see "watchdog timer", page 93) 0= disables the watchdog timer b1 b1-channel processing 1= enables the microprocessor to access b1-channel data between iom ? -2 and the transceiver core 0= disables the function described above b2 b2-channel processing 1= enables the microprocessor to access b2-channel data between iom ? -2 and the transceiver core 0= disables the function described above d d-channel processing 1= enables the microprocessor to access d-channel data between iom ? -2 and transceiver core 0= disables the function described above ci c/i-channel processing 1= enables the microprocessor to access c/i-commands and indications between iom ? -2 and transceiver core 0= disables the function described above mon monitor-channel processing 1= enables the microprocessor to access monitor-channel messages at iom ? -2 and at the transceiver core 0= disables the function described above peb 2091 pef 2091 register description semiconductor group 221 data sheet 01.99 5.2.13 b-channel access registers 5.2.14 d-channel access registers bs bs bit operates in combination with swst:sgl and adf:cbac bits to control the s/g bit and the bac bit. for the functional description see "indication of s/g bit status on pin sg", page 205 sgl stop/go operates in combination with swst:bs and adf:cbac bits to control the s/g bit and the bac bit. for the functional description see "indication of s/g bit status on pin sg", page 205 register value after reset (hex) function address (hex) wb1u 00 write b1-channel data to transceiver core 6 rb1u 00 read b1-channel data from transceiver core 6 wb1i 00 write b1-channel data to iom ? -2 8 rb1i 00 read b1-channel data from iom ? -2 8 wb2u 00 write b2-channel data to transceiver core 7 rb2u 00 read b2-channel data from transceiver core 7 wb2i 00 write b2-channel data to iom ? -2 9 rb2i 00 read b2-channel data from iom ? -2 9 register value after reset (hex) function address (hex) dwu ff write d-channel data to transceiver core 3 dru ff read d-channel data from transceiver core 3 dwi ff write d-channel data to iom ? -2 b dri ff read d-channel data from iom ? -2 b peb 2091 pef 2091 register description semiconductor group 222 data sheet 01.99 5.2.15 monitor-channel access registers register value after reset (hex) function address (hex) mox ff monitor data transmit register 2 mor ff monitor data receive register 2 peb 2091 pef 2091 programming semiconductor group 223 data sheet 01.99 6 programming this chapter contains a summery of commands and indications used to program the iec-q. an overview of the following codes is given ? c/i channel commands and indications ? predefined monitor channel messages ? predefined eoc messages furthermore, several examples for programming codes are given. this includes ? programming code for the c/i and the monitor channel in the microprocessor mode (sections 6.4 and 6.5) ? programming code for the power controller interface, which applies only in stand-alone mode (section 6.6) ? programming code for test loop-backs (section 6.7) ? programming code for activation and deactivation control for all important configurations (section 6.8) note 65: programming the c/i channel and the monitor channel can be performed using either the iom ? -2 interface, which is available in every mode, or the p interface if the p mode is used. a combination of both is also possible in the p mode. for information about the iom ? -2 interface characteristics, see "iom ?-2 interface", page 70. see also "microprocessor access to iom?-2 channels", page 97, for the p mode. peb 2091 pef 2091 programming semiconductor group 224 data sheet 01.99 6.1 c/i channel codes both commands and indications depend on the iec-q mode and the data direction. table 38 gives all defined c/i-codes. table 39 shows the abbreviations used for c/i-commands and indications. table 38 command / indicate codes code nt mode lt mode in out in out 0000 tim dr dr C 0001 res C res deac 0010 C fj 1) 1) in nt-pbx mode only Cfj 0011 du 2) 2) du is only used in the repeater Cltdhi 0100 ei1 ei1 res1 rsy 0101 ssp C ssp ei2 0110 dtintdtint 0111 C pu uar uai 1000 ar ar ar ar 1001 C C arx arm 1010 arl arl arl C 1011 C C C ei3 1100 ai ai C ai 1101 C C ar0 lsl 1110 C ail C C 1111 di dc dc di peb 2091 pef 2091 programming semiconductor group 225 data sheet 01.99 table 39 c/i-abbreviation code description ai activation indication ar activation request ar0 activation request with act bit = 0 arl activation request local loop arm activation request maintenance bits arx activation request with timer t1 [15 sec.] ignored dc deactivation confirmation dr deactivation request deac deactivation accepted di deactivation indication dt data-through test mode du deactivation request upstream ei1 error indication1 (error on u) ei2 error indication2 (error on s/t) ei3 error indication3 (time-out t1 [15sec] error on u) fj frame jump hi high impedance (set by pin "ps1") int interrupt (set by pin "int") ltd lt disable (control of pin "diss") lsl loss of signal level on u uai u-activation indication uar u-activation request res reset res1 reset receiver rsy loss of synchronization pu power-up ssp send-single-pulses test mode tim timing request peb 2091 pef 2091 programming semiconductor group 226 data sheet 01.99 6.2 monitor channel codes 4 categories of monitor messages are supported by the iec-q: C mon-0 (eoc programming) C mon-1 (maintenance bits, s/q-channel) C mon-2 (overhead bits) C mon-8 (local functions) 6.2.1 mon-0 codes addr: address C 0 = nt C 1 6 = repeater C 7 = broadcast d/m: data/message C 0 = data C 1 = message e: eoc code C 00 ff h = coded eoc command/indication table 40 format of mon-0-commands 1. byte 2. byte 0 0 0 0 a a a | 1 e e e e e e e e mon-0 addr. | d/m eoc code table 41 predefined mon-0 commands and indications mon-0-functions code hex. nt lt function dudu 00 h h hold 50 lbbd lbbd close complete loop 51 lb1 lb1 close loop b1 52 lb2 lb2 close loop b2 53 rcc rcc request corrupt crc 54 ncc ncc notify of corrupt crc aa utc unable to comply ff rtn rtn return to normal xx ack acknowledge peb 2091 pef 2091 programming semiconductor group 227 data sheet 01.99 6.2.2 mon-1 codes s/q: s/q-channel C 00 ff h = coded s/q-command indication m: maintenance bits C 00 ff h = set/reset maintenance bits the following indications and maintenance bits are defined in mon-1-messages. table 42 format of mon-1 messages 1. byte 2. byte 0 0 0 1 0 0 0 0 s s s s m m m m mon-1 s/q-code m-bits table 43 mon-1 s/q-channel commands and indications mon-1-functions s/q nt lt-rp function (bin) dudu s/q-channel 0 0 0 1 st 1) self-test request 0 0 1 0 stp 1) self-test pass. 0 1 0 0 febe febe far-end block error. 1 0 0 0 nebe nebe near-end block error. 1 1 0 0 fnbe fnbe far and near-end block error. 1 1 1 1 norm 1) table 44 mon-1 m-bit commands mon-1-functions m-bit nt lt function (hex) dudu m-bit-channel 1 x x 0 ntm 1) 1) these messages are used in nt , nt-pbx, and te modes only nt test mode 1 1 1 1 norm 1) normal peb 2091 pef 2091 programming semiconductor group 228 data sheet 01.99 6.2.3 mon-2 codes d0 11: overhead bits. 6.2.4 mon-8 codes r: register address C 0 = local function register C 1 = internal register d07 local command C 00 ff h = local function code C 00 ff h = internal register address the following local commands are defined. table 45 format of mon-2-messages 1. byte 2. byte 0 0 1 0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mon-2 overhead bits overhead bits table 46 format of mon-8-messages 1. byte 2. byte 1 0 0 0 r | 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 mon-8 register | addr. local command (message/data) peb 2091 pef 2091 programming semiconductor group 229 data sheet 01.99 table 47 mon-8-local function commands mon-8-functions r code nt lt function (bin) dudu 0 1000 1110 tll 1) tll 1) a change in at least one of the m4 bits will be passed via mon-2 only after valid triple last look 0 1000 1101 crc 2) crc 2) a change in at least one of the m4 bits will be passed via mon-2 only if the crc is valid for the last two superframes, not including the current one. 0 1000 1111 tll, crc tll, crc a change in at least one of the m4 bits will be passed via mon-2 only after valid triple last look, and if the crc is valid for the last two superframes, not including the current one 0 1000 1100 on change on change every change in at least one of the m4 bits will be passed via mon-2 0 1000 1010 tll 1) tll 1) a change in at least one of the additional overhead bits will be passed via mon-2 only after valid triple last look. 0 1000 1001 crc 2) crc 2) a change in at least one of the additional overhead bits will be passed via mon-2 only if the crc is valid for the last two superframes, not including the current one. 0 1000 1011 tll, crc tll, crc a change in at least one of the additional overhead bits will be passed via mon-2 only after valid triple last look, and if the crc is valid for the last two superframes, not including the current one 0 1000 1000 on change on change every change in at least one of the additional overhead bits will be passed via mon-2 0 1011 1110 pace pace partial activation control external 0 1011 1111 paca paca partial activation control automatic 0 1111 0000 ccrc 3) ccrc corrupt crc 0 1111 0100 lb1 3) loop b1 peb 2091 pef 2091 programming semiconductor group 230 data sheet 01.99 definitions: a a power controller address to pins pca b b internal coefficient value c c internal coefficient address d d power controller data to/from pins pcd r r result from block error counter v v power feed current value 0 1111 0010 lb2 3) loop b2 0 1111 0001 lbbd 4) loop b1 + b2 + d 0 1111 1111 norm 3) norm return to normal 0 1111 1011 rben rben read near-end block error counter 0 1111 1010 rbef rbef read far-end block error counter 0 r r r r r r r r abec abec answer block error counter 0 1111 1000 rpfc read power feed current 0 vvvv vvvv apfc answer power feed current 0 011d ddaa wci 5) wci 5) write controller interface 0 010* * * * rci 5) rci 5) read controller interface 0 ddd* **** aci 5) aci 5) answer controller interface 0 0000 0000 rid rid read identification 0 **** **** aid aid answer identification. the iec-q version 5.3 will reply with the id 8003 h 0 1111 1001 sfb sfb set febe-bit to (0) 1 cccc cccc rcoef rcoef read coefficient 1 1 bbbb bbbb bbbb bbbb dcoef dcoef data coefficients, 2 bytes. data bits d0 d 7, 1. byte data bits d8 d15, 2. byte 6) 1) default setting after reset in non repeater modes 2) default setting after reset in repeater modes 3) used in eoc transparent mode only 4) this code is used in eoc transparent mode or in eoc auto mode after the receipt of "lbbd" in the eoc-channel 5) see power controller interface description 6) the first byte of the corresponding mon-8 message will be "10001100" table 47 mon-8-local function commands mon-8-functions peb 2091 pef 2091 programming semiconductor group 231 data sheet 01.99 6.3 predefined eoc codes the eoc contains an address field, a data/message indicator and an eight-bit information field, see "u -frame structure", page 67 for details. the data/message indicator needs to be set to (1) to indicate that the information field contains a message. if set to (0), numerical data is transferred to the nt. currently no numerical data transfer to or from the nt is required. from the 256 codes possible in the information field 64 are reserved for non-standard applications, 64 are reserved for internal network use and eight are defined by ansi for diagnostic and loop-back functions. all remaining 120 free codes are available for future standardization. table 48 supported eoc-commands eoc address field data/ message indicator information o (rigin) d (estination) message a1a2a3 d/m i1 i2 i3 i4 i5 i6 i7 i8 lt nt 000 x nt 111 x broadcast 0 01 1 10 x repeater stations no. 1 C no. 6 0data 1 message 1 01010000 o d lbbd 1 01010001 o d lb1 1 01010010 o d lb2 1 01010011 o d rcc 1 01010100 o d ncc 1 11111111 o d rtn 1 00000000 d/o o/d h 1 101 01010 d o ack peb 2091 pef 2091 programming semiconductor group 232 data sheet 01.99 6.4 example for c/i channel programming note 66: this example applies only in p-nt mode. figure 91 example: c/i-channel use (all data values hexadecimal) itd10291 m p ciwu = c7 ista = 02 ciru = 03 cicu c/i channel handler transmit c/i- command "res" new c/i-code received from u read new c/i-code. c/i = 0000b = c/i = 0001b u-transceiver transfer to "test" state send c/i-indication "dr" interrupt peb 2091 pef 2091 programming semiconductor group 233 data sheet 01.99 6.5 example for monitor channel programming note 67: this chapter applies only in p mode. the example on page 234 illustrates the read-out of the transceivers identification number (id). it consists of the transmission of a two-byte message from the control unit to the transceiver in iom ? -2 channel 0. the transceiver acknowledges the receipt by returning a two-byte long message in the monitor channel. the procedure is absolutely identical for monitor channel 1. the m p starts the transfer procedure after having confirmed that the monitor channel is inactive. the first byte of monitor data is loaded into the transmit register mox. via the monitor control register mocr monitor interrupts are enabled and control of the mx-bit is handed over to the iec-q. then transmission of the first byte begins. the transceiver core reacts to a low level of the mx-bit by reading and acknowledging the monitor channel byte automatically. on detection of the confirmation, the iec-q issues a monitor interrupt to inform the m p that the next byte may be sent. loading the second byte into the transmit register results in an immediate transmission (timing is controlled by the iec-q). the transceiver core receives the second byte in the same manner as before. when transmission is completed, the transceiver core sends "end of message" (mx-bit high). it is assumed that a monitor command was sent that needs to be answered by the transceiver core (e.g. read-out of a register). therefore, the transceiver core commences to issue a two-byte confirmation after an end-of-message indication from the iec-q has been detected. the iec-q notifies the m p via interrupt when new monitor data has been received. the processor may then read and acknowledge the byte at a convenient instant. when confirmation has been completed, the transceiver core sends "eom". this generates a corresponding interrupt in the iec-q. by setting the mr-bit to high, the monitor channel is inactive, the transmission is finished. peb 2091 pef 2091 programming semiconductor group 234 data sheet 01.99 example: monitor channel transmission and reception basic configuration, iom ? -2 clocks must be active w stcr = 0x15 // te mode, eoc auto mode w swst = 0x0c // access to c/i and monitor channel w adf2 = 0x48 // monitor access to transceiver core transmission r mosr = 0x00 // transmission inactive (mac = 0) w mox = 0x80 // mon-8 command w mocr = 0x30 // transmit command r ista = 0x11 // monitor mda interrupt r mosr = 0x28 // ackn. indication w mox = 0x00 // access to register 0 r ista = 0x11 // monitor mda interrupt r mosr = 0x28 // ackn. indication reception w mocr = 0x80 // enable receive of monitor message r ista = 0x08 // monitor mdr interrupt r mosr = 0x80 // data received r mor = 0x80 // value read monitor 8 command ind. w mocr = 0xc0 // acknowledge reading r ista = 0x08 // monitor mdr interrupt r mosr = 0x80 // data received r mor = 0x03 // data from register 0 (identification) r ista = 0x08 // monitor mdr interrupt r mosr = 0x40 // eom received w mocr = 0x80 // enable interrupts. peb 2091 pef 2091 programming semiconductor group 235 data sheet 01.99 6.6 example for programming power controller interface note 68: this chapter applies only in stand-alone mode. assumption: the address lines are not connected, the data lines are clamped to the values given in the application. 1. write to controller interface: iom ? -2 iec-q a) mon-8 wci (80 7c) CCCC> pin pca0 = (0) ; write data 7 h to address pin pca1 = (0) ; 0 h pin pcd0 2 = (1) ; data not latched b) mon-8 wci (80 62) CCCC> pin pca0 = (0) ; write data 0 h to address pin pca1 = (1); 1 h pin pcd0 2 = (0) ; data not latched 2. read from controller interface: iom ? -2 iec-q a) pin pcd0 = (0) ; values stable on data port pin pcd1 = (0) pin pcd2 = (0) mon-8 rci (80 40) CCCC> pin pca0 = (0) ; read from address 0 h pin pca1 = (0) ; address is latched mon-8 aci (80 00) peb 2091 pef 2091 programming semiconductor group 237 data sheet 01.99 6.7.2 examples for complete loop-back #2 control the typical procedure for closing and opening a complete loop-back is demonstrated in the examples below. complete loop-back in eoc auto mode in the above example the lt is operated in eoc auto mode. nt lt c/i ar (1000 b ) peb 2091 pef 2091 programming semiconductor group 238 data sheet 01.99 complete loop-back in eoc transparent mode in the above example the lt is operated in eoc auto mode. nt lt CCCCC> c/i ai (1100 b ) c/i ar (1000 b ) peb 2091 pef 2091 programming semiconductor group 239 data sheet 01.99 6.7.3 examples for single channel loop-back #2 control the typical procedure for closing and opening a single channel loop-back is demonstrated in the examples below. single-channel loop-back in eoc auto mode in the above example the lt is operated in eoc auto mode. nt lt CCCCC> c/i ai (1100 b ) c/i ar (1000 b ) peb 2091 pef 2091 programming semiconductor group 240 data sheet 01.99 single-channel loop-back in eoc transparent mode in the above example the lt is operated in eoc auto mode. nt lt CCCCC> c/i ai (1100 b ) c/i ar (1000 b ) peb 2091 pef 2091 programming semiconductor group 241 data sheet 01.99 6.8 examples for activation and deactivation control codes 6.8.1 complete activation initiated by lt activation initiated by ar activation initiated by arx nt lt peb 2091 pef 2091 programming semiconductor group 242 data sheet 01.99 6.8.2 complete activation initiated by te when initiating an activation from the terminal side, the lt must be in the "deactivated" state. for a te initiated activation to be successful the downstream lt c/i-code must be dc. this is not the case if the "deactivated" state has been entered from the "test" state (the last code is dr in this case). nt lt peb 2091 pef 2091 programming semiconductor group 243 data sheet 01.99 6.8.3 activation with act-bit status ignored by exchange side the lt ignores the act-bit transmitted upstream from the nt if the lt activation has been initiated with ar0 instead of ar. because the activation with ar0 is performed with the uoa-bit set to "0", initially only a partial activation is started. by setting uoa = 1 via a mon2 message the s-interface is activated as well. 6.8.4 complete deactivation deactivating the u-interface can be initiated only by the exchange. a deactivation can be started when the device is in the states "line active", "pend. transparent" , "transparent" or "s/t deactivated" . nt lt peb 2091 pef 2091 programming semiconductor group 245 data sheet 01.99 6.8.7 complete activation initiated by te with u active when the terminal requests to activate the s-interface (u-interface already active) two cases can occur: in the first case the exchange has retained control over the s-interface activation. then s-activation can proceed only after the explicit permission by the exchange with ar. this situation is discussed in this section under "case 1". in the second case the exchange is not requested to send ar in order to continue activation. this situation is described in "case 2" of this section. the terminal recognizes no difference between the two types, the procedure on nt side consequently is identical in both cases. case 1 (controlled by exchange) case 2 (no control by exchange) nt lt peb 2091 pef 2091 programming semiconductor group 246 data sheet 01.99 6.8.8 deactivating s/t-interface only the following example shows the procedure for deactivating the s-interface only while leaving the u-interface active. 6.8.9 activation initiated by lt with repeater for lt and nt the activation procedure with a repeater between exchange and network is identical to that described at the beginning of this chapter. the repeater transforms the received u-signals into c/i-codes and monitor messages. these codes and messages pass the repeater control unit (e.g. p). in this control unit a number of adaptations are made to comply with a specific national specification. in this section only c/i-codes are considered which need to be transformed by the control unit such that the repeater counterpart will operate correctly. in addition overhead bits and the specified 2b+d data needs to be transferred for a correct repeater activation/deactivation. in order to recognize the dependence of lt-rp and nt-rp-signals more easily, the arrows point towards the middle. when activating the repeater unit from the exchange side, the uai-code issued by the lt-rp needs to be converted into ai for the nt-rp. nt lt peb 2091 pef 2091 application hints semiconductor group 249 data sheet 01.99 7.1 external circuitry 7.1.1 power supply blocking recommendation the following blocking circuitry is suggested. figure 92 power supply blocking 1) 2) v dda2 v dda1 v dda1 v ddd v ddd gndd gnda1 gnda2 1) 2) 1) 2) 3) 220 f 1 f 100 nf 100 nf 100 nf 1) these capacitors should be located as near as possible to the pins 2) mkt-stack film capacitors 3) tantanum electrolytic capacitor peb 2091 pef 2091 application hints semiconductor group 250 data sheet 01.99 7.1.2 u-interface note 70: the requirements for the power spectral density of the transmitted 2b1q signal on the u-interface has been changed by etsi. this change aims to reduce interference between basic rate 2b1q signals on the one hand and adsl and vdsl signals on the other. all of these signals will be transmitted on the same kind of lines in the future. for more information, refer to the etsi document technical specification 101080" (1999). to meet the new specification some modifications of the hybrid recommended in previous iec-q versions are required. figure 93 below illustrates the hybrid circuit needed to meet these new etsi requirements. note 71: this change will be in force from january, 2000 onward. after this date systems with the old hybrid will not comply to etsi standards at this point. figure 93 u-interface hybrid circuit 3 1 f $287 %287 u 22 nf $,1 %,1 22 nf 22 nf 24 w 619 w 10 k w 6.8 nf c k 10 k w 681 w 3.01 k w 619 w 24 w 10 k w 10 k w 1:1.6 peb 2091 pef 2091 application hints semiconductor group 251 data sheet 01.99 note 72: the three 22 nf capacitors can be replaced by one 33 nf capacitor in the middle. however, the solution with the three capacitors can absorb longitudinal disturbances in a better way. to improve transmission performance the following recommendations should be considered in circuit design: ? all capacitors of the hybrid should be mkt. ceramic capacitors are not recommended ? do not cross hybrid or xtal with clock lines ? analog lines between transformer and chip should be symmetric and close together so that noise is inducted symmetrically ? hybrid layout should be symmetric ? if possible there should be a ground plane underneath the iec-q ? blocking of vdd according to recommendation and as close as possible to device (see also "power supply blocking recommendation", page 249). ? tolerances resistors: 1% 6.8 nf: 5% 22 nf: 5% peb 2091 pef 2091 application hints semiconductor group 252 data sheet 01.99 7.1.3 oscillator circuit and crystal figure 94 illustrates the recommended oscillator circuit. a crystal or an oscillator signal may be used. figure 94 crystal oscillator or external clock source crystal parameters frequency: 15.36 mhz load capacitance c l : 20 pf 0.3 pf frequency tolerance: 60 ppm resonance resistance: 20 w max. shunt capacitance: 7 pf drive current i q 1 ma maximum drive current i qmax 2 ma motional capacitance 20 ff 20% motional inductance ? 9.4 mh oscillator mode: fundamental note 73: typical values for capacitances connected to the crystal are 22 ... 33 pf, depending on board layout. n.c. 15.36 mhz oscillator signal from external source xout xin xout xin c ld c ld 15.36 mhz c ld = 2 x c l - c i/o peb 2091 pef 2091 application hints semiconductor group 253 data sheet 01.99 note 74: these parameter shall apply to the complete temperature range and life time. the temperature range depends on the version used. for peb 2091 it is between 0c and 70c, for the pef 2091 it is between -40c and 85c. external oscillator frequency: 15.36 mhz frequency tolerance: 80 ppm in this case the requirements for the master clock are the same as the requirements in the lt case. see "master clock", page 281 for details. 7.2 applications with epic ? on the line card (pbx) this section gives an example for using the s/g bit and bac bit control feature (see section 3.9, page 90) for d-channel arbitration in pbx applications with the peb 20550 (elic ? ) used in the line card. the s/g bit on dout (downstream) and the bac bit on din (upstream) can be used to allow d-channel arbitration similar to the operation of the upn interface realized with the octat-p and the isac ? -p te. the basic function is as follows: the pbx line card using the elic ? assigns one hdlc controller to a number of terminals. as soon as one terminal t requests the d-channel, e.g. for signalization, all other terminals receive a message indicating the d-channel to be blocked for them. the request is done with the bac bit. at terminal t the bac bit is set and the iec-q transfers the need for the d-channel to the lt side. there, the hdlc-controller is assigned to the appropriate iom ? -2-channel. once this is done and indicated to the terminal by means of the s/g bit, the terminal begins to send d-channel messages. note that this procedure is somewhat different from the operation of the octat-p used with the isac ? -p te. there, the begin of the upstream d-channel data transfer itself indicates the need for the hdlc-controller. this implies that any other terminal, that incidentally sent a hdlc-message the same time, can be stopped before the message is lost in case the hdlc-controller is not available. the u-interface featured by the iec-q is not able to transfer the available/blocked information often enough to ensure this. hence, it is necessary to indicate a d-channel access by the terminal in advance. "in advance" actually means about 14 ms. giving mon-0 25 h at the lt during transparent operation will cause the d-channel access at the nt side to be on "stop". as one eoc-message is transmitted via the eoc-channel once every 6 ms, the s/g bit on iom ? -2 can be set in 6 ms intervals. if the 4 channel peb 24911 (dfe-q) is used in the lt, a peb 20550 (elic ? ) can arbitrate the d-channel via the c/i command as known from the octat-p and quat-s devices. please refer to the peb 24911 data sheet for detailed information on this. peb 2091 pef 2091 application hints semiconductor group 254 data sheet 01.99 the bac bit together with the eoc-messages received from the lt control the s/g bit and the upstream d-channel according to table 49. . d-channel request by the terminal figure 95, page 256, illustrates the request for the hdlc-controller by the terminal. the start state is bac = 1 at din after td1 has expired. that causes the s/g bit to be set to the stop position. bac = 1 received on din sets the s/g bit on dout to the stop position (1) at the next iom ? -2-frame. when the terminal requests access to the hdlc-controller in the elic ? it sets the bac-bit at din of its iec-q to "0". that causes the d-channel data upstream to be tied to "0" and the s/g-bit to be set to "1". the elic ? receives the zeros and reacts by assigning the hdlc-controller to this very terminal. this is indicated via the change of c/i code downstream at the lt side resulting in the s/g bit to be set to "0" (go) after delay td1 (see below for the explanation of td1 and td2). the iec-q will continue to send "0" upstream in the d-channel until the hdlc data arrives at din. the hdlc-frame itself, marked by the first "0" in the d-channel will reset the d-channel back to transparent. this allows to have arbitrary delays between the s/g bit going to "0" and the d-channel being used without the risk of loosing the hdlc-controller by sending an abort request consisting of all "1". at the end of the hdlc-frame the bac bit is reset to "1" again by the layer-2 controller (e.g. smartlink; icc). this causes the s/g bit to be set to "1" in the next iom ? -2 frame which stops a possible second hdlc-frame that could not be processed in the elic ? anymore. td1 and td2 the delays td1 and td2 (see figure 95, page 256) have the following reasons: td2 is caused by the 6ms interval in which an eoc message can be transmitted on the table 49 control structure of the s/g bit and of the d-channel bac bit of last iom ? -2-frame s/g bit 1 = stop 0 = go d-channel upstream 0 reflects last received eoc message after falling edge after delay td1 (1.5 ms and two eoc-frames) tied to "0" 1 1 set transparent with first "0" in d-channel peb 2091 pef 2091 application hints semiconductor group 255 data sheet 01.99 u-interface. as an eoc-message can start once every 6 ms and will take 6 ms to be transmitted, td2 will be 12 ms in the worst case. td1 is at minimum 7.5 ms depending on the location of the superframe at the time the hdlc-controller is requested by the terminal. this delay is necessary because instead of receiving an eoc-message "go" as requested, the terminal could as well receive the eoc message "stop" because the hdlc-controller was assigned to an other subscriber just before . flags as interframe fill the influence to the upstream d-channel can be disabled while the control of the s/g-bit via eoc-messages and via the bac bit is still given as described above by setting swst:bs to "0", swst:sgl to "1" and adf:cbac to "1". this is useful when having a controlling device in the terminal, that is able to send the interframe timefill "flags". peb 2091 pef 2091 application hints semiconductor group 256 data sheet 01.99 figure 95 d-channel request by the terminal itd08122 elic afe/dfe iec-q iec-q v5.1 te mode u k0 c/i = xxxx 1 = bac s/g = 1 d-channel transparent 1100 = c/i bac = 0 hdlc occupied by other terminal: d-channel fied to "0" delay td1 delay td2 "00" on d-channel eoc 25 h delay td2 hdlc assigned: c/i = 1000 h 27 eoc hdlc-controller available transparent; = s/g hdlc-frame on d-channel d-channel transparent frame hdlc bac = 1 eoc 25 h 1100 = c/i hdlc ready: delay td2 d-channel transparent 1; = s/g "stop" r iom -2 r r iom -2 peb 2091 pef 2091 application hints semiconductor group 257 data sheet 01.99 7.3 hints for repeater applications 7.3.1 eoc addressing management note 75: access to eoc is described in detail in "access to eoc of u-interface", page 110. this application hint describes a way of addressing a certain repeater if one or more repeater are used in one transmission line. the lt-rp and nt-rp should be operated in eoc transparent mode (see "eoc auto/transparent mode", page 55). in order to address each repeater individually, the eoc-addresses (001 b ) to (110 b ) are used. this allows a maximum of 6 repeater stations to be addressed. the repeater address is 001 b . if a repeater control unit detects an eoc-message with this address, the eoc-command will be executed according to the national repeater specification. in case an eoc-message with the nt (000 b ) or broadcast (111 b ) address is received by the repeater, the message needs to be passed on without modifications. if any other address is received (i.e. (010 b ) to (110 b )) the repeater control unit (p or asic) decrements the address before passing the eoc-message downstream. figure 96 illustrates this procedure with a repeater and a nt eoc-address. figure 96 eoc-handling in repeater applications itd04216 nt lt rp nt rp m p repeater # 3 ~ ~ uu ~ ~ 2 # repeater p m rp nt rp lt u ~ ~ 1 # repeater p m rp nt rp lt ~ ~ u lt eoc processing eoc processing adr = 1 2 = adr 3 = adr adr = 0 adr = 0 0 = adr 0 = adr eoc adr = 3 0 = adr eoc peb 2091 pef 2091 application hints semiconductor group 258 data sheet 01.99 7.3.2 single bits handling figure 97 shows an example for typical maintenance bit handling in repeater applications via mon-2. in this example a microprocessor can be used as a control unit and the microprocessor interface can be used instead of the iom ? -2 interface. figure 97 maintenance bit handling in repeaters (example) itd04217 act dea uoa m43 44 m 45 m 46 m 48 m 51 m 52 m 61 m febe act ps 1 ps 2 ntm cso sai m61 m52 m51 m48 m46 crc febe crc & & mon-1 mon-2 mon-2 mon-2 lt nt-rp u ref. point dea m61 m52 m51 m48 m46 m45 m44 43 m uoa dea act mon-2 febe mon-2 mon-1 crc crc febe 46 m 48 m 51 m 52 m 61 m sai cso ntm 2 ps 1 ps act lt-rp nt repeater control unit u ref. point iom -2 r r -2 iom mon-2 c/i peb 2091 pef 2091 application hints semiconductor group 259 data sheet 01.99 7.4 set-ups for test modes and system measurements with a number of operational modes the iec-q supports system measurements. these modes along with the most frequently needed system measurements are described in the following sections. 7.4.1 tests in send single pulses mode the ssp-test mode is required for pulse mask measurements. in this test mode, the iec-q transmits on the u-interface alternating 3 pulses spaced by 1.5 ms. this test mode is used in lt and nt like modes. three options exist for selecting the send-single-pulses" (ssp) mode: C hardware selection: resq = 1 & tsp = 1 C software selection: c/i = ssp (0101 b ) C microprocessor selection bits (stcr:tm1 = 1) and (stcr:tm2 = 1) all methods are fully equivalent. in the ssp mode the c/i-code transmitted by the iec-q is deac in lt modes and dr in the nt modes. pulse mask measurement C pulse mask is defined in ansi t1.601 and etsi ts 101080 C u-interface has to be terminated with 135 w C iec-q is in single-pulses" mode C measurements are done using an oscilloscope 7.4.2 tests in data-through mode the dt mode is required for power spectral density and total power measurements. when selecting the data-through mode, the iec-q is forced directly into the transparent" state. this is possible from any state in the state diagram. the data-through option (dt) provides the possibility to transmit a standard scrambled u-signal even if no u-interface wake-up protocol is possible. this feature is of interest when no counter station can be connected to supply the wake-up protocol signals. the dt-test mode may be used in lt and nt like applications. as with the ssp mode, three options are available. C hardware selection: resq = 0 & tsp = 1 C software selection: c/i = dt (0110 b ) C microprocessor selection bits (stcr:tm1 = 0) and (stcr:tm2 = 1) peb 2091 pef 2091 application hints semiconductor group 260 data sheet 01.99 power spectral-density measurement C psd is defined in ansi t1.601 and etsi ts 101080 C u-interface has to be terminated with 135 w C iec-q is in data-through" mode C for measurements a spectrum analyzer is employed total power measurement C total power is defined in ansi t1.601 and etsi ts 101080 C total power must be between 13 dbm and 14 dbm C u-interface has to be terminated with 135 w C iec-q is in data-through" mode C measurements are done using an 80 khz high-impedance low-pass filter and true rms-voltmeter figure 98 total power measurement set-up insertion loss measurement C insertion loss is defined in ansi t1.601 C iec-q is in data-through mode C trigger and exit criteria have to be realized externally its04227 80 khz iec-q true rms voltmeter peb 2091 pef 2091 application hints semiconductor group 261 data sheet 01.99 7.4.3 tests in master-reset mode the master-reset test mode is used for the return-loss measurements. the master-reset mode characterizes the mode where the iec-q does not transmit any signals. the chip is in the test" state. all echo canceller and equalizer coefficients are reset. as can be seen from the state diagram, no activation is possible in lt or nt modes when the device is in the test" state. for measurements two methods are recommended in order to transfer the iec-q into the master-reset mode: C hardware selection: resq = 0 & tsp = 0 C software selection: c/i = res (0001 b ) the c/i-code transmitted by the iec-q in the test" state is deac in lt modes and dr in all nt modes. return-loss measurement C return loss is defined in ansi t1.601 and etsi ts 101080 C iec-q is in test state C measure complex impedance z" from 14 khz C 200 khz C calculate return loss with formula: rl(db) = 20log (abs((z + 135) / (z C135))) quiet mode measurement C quite mode is defined in ansi t1.601 C iec-q is in the test state C trigger and exit criteria have to be realized externally peb 2091 pef 2091 electrical characteristics semiconductor group 262 data sheet 01.99 8 electrical characteristics this chapter specifies on the one hand the electrical characteristics of device inputs and power needed to guarantee proper operation of the iec-q. on the other hand it specifies the electrical characteristics of the iec-q outputs, power consumption and analog functions. note 76: all electrical characteristics of the iec-q apply only in the specified operational range and under the stated test conditions. sections 8.1 and 8.2 describe the maximum ratings allowed and the power supply needed. section 8.3 specifies the maximal overload which can be imposed directly on the iec-q line interface, without causing device damage. sections 8.4 and 8.5 specify the power consumption and the analog functions (e.g. adc and dac performance). section 8.6 describes the dc characteristics of the iec-q. the dynamic characteristics of the microprocessor interface, the iom ? -2 interface, the power controller interface, the undervoltage detection block and device clock are given in section 8.7. 8.1 absolute maximum ratings parameter symbol limit values unit supply voltage v dd C 0.3 < v dd < 7.0 v input voltage v i C 0.3 < v i < v dd + 0.3 (max. 7) v output voltage v o C 0.3 < v o < v dd + 0.3 (max 7) v max. voltage applied at u-interface v s C 0.3 < v s < v dd + 0.3 (max. 7) v max. voltage between gnda1 (gnda2) and gndd v s 250 mv storage temperature t stg C 65 to 125 c ambient temperature peb 2091 pef 2091 t a t a 0 to 70 C 40 to 85 c c thermal resistance (system-air) (system-case) r th sa r th sc 40 9 k/w k/w peb 2091 pef 2091 electrical characteristics semiconductor group 263 data sheet 01.99 note 77: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. exposure to conditions beyond those indicated in the recommended operational conditions of this specification may affect device reliability. this is a stress rating only and functional operation of the device under those conditions or at any other condition beyond those indicated in the operational conditions of this specification is not implied. it is not implied, that more than one of those conditions can be applied simultaneously. 8.2 power supply supply voltages v ddd = + 5 v 0.25 v v dda1 = + 5 v 0.25 v v dda2 = + 5 v 0.25 v the maximum sinusoidal ripple on v dda1 and v dda2 is specified in the following figure: figure 99 maximum sinusoidal ripple on supply voltage itd04269 10 20 30 80 100 frequency/khz 10 20 40 100 mv 1000 frequency ripple supply voltage ripple note: the supply voltage ripple in measured peak to peak peb 2091 pef 2091 electrical characteristics semiconductor group 264 data sheet 01.99 8.3 line overload protection the maximum input current (under overvoltage conditions) is given as a function of the width of a rectangular input current pulse as outlined in the following figure. figure 100 test condition for maximum input current line input current the destruction limits for aout, bout, ain and bin are given in figure 101. figure 101 u transceiver input current its04532 i t device under test condition: all other pins grounded t wi itd09846 0.005 5 10 -9 -3 10 -1 10 1 s a wi t i 0.01 0.1 1 peb 2091 pef 2091 electrical characteristics semiconductor group 265 data sheet 01.99 8.4 power consumption the power consumption of version 5.3 has been reduced, compared with version 5.1. version 5.3 will have the same power consumption values as version 5.2. all measurements with random 2b + d data in active states. note 78: the power consumption specified above includes the power dissipation in the load resistance. the power dissipation in the iec-q itself is 7.5 ma less in the active state, i.e. the maximum internal power dissipation of the iec-q in the active state is less than 52 ma, under the stated conditions. mode test conditions limit values unit typ. max. power up 5.00 v, open outputs 98 w load at aout/bout inputs at vdd/gnd 53.059.0ma lt-power down 5.00 v, open outputs 98 w load at aout/bout temperature 3 0 c inputs at vdd/gnd 6.7 11.0 ma 5.00 v, open outputs 98 w load at aout/bout temperature < 0 c inputs at vdd/gnd 8.0 13.0 ma nt-power down 5.00 v, open outputs 98 w load at aout/bout temperature 3 0 c inputs at vdd/gnd 4.7 9.0 ma 5.00 v, open outputs 98 w load at aout/bout temperature < 0 c inputs at vdd/gnd 6.5 11.0 ma peb 2091 pef 2091 electrical characteristics semiconductor group 266 data sheet 01.99 8.5 analog characteristics limit values min. typ. max. unit receive path signal / n+d (noise + total harmonic distortion) 1) 1) test conditions: 1.3 vpp antisemetric sine wave as input on ain/bin with long range (low, critical range) 60 65 db dc-level at ad-output 45 50 55 % 2) 2) the percentage of the "1"-values in the pdm-signal threshold of level detect 4 20 28 mv input impedance ain/bin 50 k w transmit path signal / n+d (noise + total harmonic distortion) 3) 3) interpretation and test conditions: the sum of noise and total harmonic distortion, weighted with a low pass filter 0 to 80 khz, is at least 65 db below the signal for an evenly distributed but otherwise random sequence of + 3, + 1, C 1, C 3 65 70 db output dc-level 2.05 2.375 2.6 db offset between aout and bout 35.5 mv signal amplitude 4) 4) the signal amplitude measured over a period of 1 min. varies less than 1% 3.10 3.20 3.30 v output impedance aout/bout: power-up power-down 2 6 4 12 w w peb 2091 pef 2091 electrical characteristics semiconductor group 267 data sheet 01.99 pulse shape the pulse mask for a single positive pulse measured between aout and bout at a load of 98 w is given in the following figure. figure 102 pulse mask for a single positive pulse itd04267 0t 0.5 t -0.5 t -0.75 t 16 mv mv -16 -16 mv mv 16 50 t 0.1 v 3.3 v 3.2 v 3.1 v -0.4 t t 12.5 m s t= +0.4 peb 2091 pef 2091 electrical characteristics semiconductor group 268 data sheet 01.99 8.6 dc characteristics v dd = 4.75 to 5.25 v parameter symbol limit values unit test condition min. max. h-level input voltage v ih 2.0 v dd + 0.3 v l-level input voltage v il 0.8 v l-level input leakage current for all pins except for pin #11, #14, #15 i il C 10 m a v i = dgnd 1) 1) inputs at dvdd/dgnd h-level input leakage current for all pins except for pin #11, #14, #15 i ih 10 m a v i = dvdd 1) l-level input leakage current of pin #11 (xin) i il C 40 m a v i = dgnd 1) h-level input leakage current of pin #11 (xin) i ih 40 m a v i = dvdd 1) l-level input leakage current of pin #14, #15 (ain, bin) i il C 70 m a v i = dgnd 1) h-level input leakage current of pin #14, #15 (ain, bin) i ih 70 m a v i = dvdd 1) l-level input leakage current for pins with pull-up resistors i ilpu C 100 100 m a v i = dgnd 1) h-level input leakage current for pins with pull-up resistors i ihpu C 10 10 m a v i = dvdd 1) l-level input leakage current for pins with pull-down resistors i ilpd C 30 30 m a v i = dgnd 1) h-level input leakage current for pins with pull-down resistors i ihpd 500 m a v i = dvdd 1) h-level output voltage for all outputs except dout v oh1 2.4 v i oh1 = 0.4 ma 1) h-level output voltage for dout 2) 2) applies only to the active channel in the tristate mode of dout (see "dout driver modes", page 53) v oh2 3.5 v i oh2 = 6 ma 1) l-level output voltage for all outputs except dout v ol1 0.4 v i ol1 = 2 ma 1) l-level output voltage for dout v ol2 0.5 v i ol1 = 7 ma 1) peb 2091 pef 2091 electrical characteristics semiconductor group 269 data sheet 01.99 pin capacitances 8.7 ac characteristics inputs are driven to 2.4 v for a logical "1" and to 0.4 v for a logical "0". timing measurements are made at 2.0 v for a logical "1" and 0.8 v for a logical "0". the ac testing input/output wave forms are shown in figure 103 below. figure 103 input/output wave form for ac tests 8.7.1 microprocessor interface timing in parallel mode the microprocessor interface timing in the parallel mode has been accelerated. this allows using the iec-q in applications which demand high data transmission rates, e.g. pcm-4, 8, or in applications with high speed microcontroller. t a = 25 c; v dd = 5 v 5%; v ss = 0 v; f c = 1 mhz pin symbol limit values unit min. max. din, ps1, ps2, dcl (input), fsc (input), dout (open) c io 10 pf xin, xout c io 5pf all other pins c io 7pf its00621 = 150 load c test under device 0.45 2.4 2.0 0.8 0.8 2.0 test points pf peb 2091 pef 2091 electrical characteristics semiconductor group 270 data sheet 01.99 8.7.1.1 siemens/intel bus mode figure 104 siemens/intel read cycle figure 105 siemens/intel write cycle figure 106 siemens/intel multiplexed address timing itt00712 rd x cs ad0 - ad7 t rd data t df rr tt ri itt00713 wr x cs ad0 -ad7 t dw data t wd ww tt wi itt00714 wr x cs ad0 - ad7 t la cs x rd or address ale t als t al t aa t ad peb 2091 pef 2091 electrical characteristics semiconductor group 271 data sheet 01.99 figure 107 siemens/intel non-multiplexed address timing 8.7.1.2 motorola bus mode figure 108 motorola read timing figure 109 motorola write cycle itt00715 wr x cs a0 - a5 t ah t as address cs x rd or itt00716 cs x ds d0 - d7 t rd data t df dsd t rr t t ri r/w t rwd peb 2091 pef 2091 electrical characteristics semiconductor group 272 data sheet 01.99 figure 110 motorola non-multiplexed address timing 8.7.1.3 timing values of the p interface in parallel mode c load = 50pf parameter symbol min. max. unit ale pulse width t aa 50 ns address setup time to ale t al 15 ns address hold time from ale t la 10 ns address latch setup time to wr , rd t als 0ns address setup time to wr , rd t as 25 ns address hold time from wr , rd t ah 0ns ale pulse delay t ad 10 ns ds delay after r/w setup t dsd 0ns r/w hold time after ds t rwd 0ns rd pulse width t rr 110 ns data output delay from rd t rd 110 ns data float from rd t df 25 ns rd control interval t ri 70 ns wr pulse width t ww 60 ns data setup time to wr x cs t dw 35 ns data hold time from wr x cs t wd 10 ns wr control interval t wi 70 ns itt00718 cs x ds ad0 t ah t as - ad5 peb 2091 pef 2091 electrical characteristics semiconductor group 273 data sheet 01.99 8.7.2 serial microprocessor interface timing the following 2 figures describe the read/write cycles and the corresponding address timing for the serial microprocessor interface: figure 111 serial p interface mode write figure 112 serial p interface mode read 1 a3 a2 a1 a0 x d7 x x d6 d5 d4 d3 d2 d1 d0 css t p t cdins t cs cclk cdin cdout high z cdinh t csh t 0 a3 a2 a1 a0 x d7 xx d6 d5 d4 d3 d2 d1d0 cdin cdout high z cdoutd t css t p t cs cclk csh t peb 2091 pef 2091 electrical characteristics semiconductor group 274 data sheet 01.99 8.7.3 iom ? -2 interface timing note 79: in case the period of signals is stated the time reference will be at 1.4 v; in all other cases 0.8 v (low) and 2.0 v (high) thresholds are used as reference. via the iom ? -2-interface data is transmitted in both directions (du and dd) at half the data clock rate. the data clock (dcl) is a square wave signal with a duty cycle ratio of typically 1:1. incoming data is sampled on the falling edge of the dcl-clock. figure 113 iom ? -2 interface timing the dynamic characteristics of the iom ? -2-interface is given in the following figure 114 where detail "a" of figure 113 is shown in more detail. table 50 timing characteristics (serial p interface mode) c load = 50pf parameter symbol min. max. unit clock period t p 130 ns chip select setup time t css 0ns chip select hold time t csh 20 ns cdin setup time t cdins 40 ns cdin hold time t cdinh 40 ns cdout data out delay t cdoutd 30 ns itd04228 "a" bit 32 bit 0 bit 1 bit 2 dcl fsc du dd peb 2091 pef 2091 electrical characteristics semiconductor group 275 data sheet 01.99 figure 114 iom ? -2 timing of iom ? -2 interface (detail) table 51 iom ? -2 dynamic input characteristics parameter signal symbol limit values unit min. max. data clock rise/fall dcl t r , t f 60 ns clock period t dcl 200 ns pulse width high/low t wh t wl 53 53 ns ns frame synch. rise/fall fsc t r , t f 60 ns frame setup t sf 30 ns frame hold t df t wl C 30 ns frame width high/low 1) 1) this is in according to the iom ? -2-timing specification. for correct functional operation the high period must be 1 t dcl for superframe markers and at least 2 t dcl for non-superframe markers t wfh t wfl 100 2 t dcl ns data sample delay din t sd t wh + 20 ns data hold t hd 50 ns t r f t t wh t dcl wl t ddc t t ddf t wfh t sf df t t hd sd t dcl fsc dout din data valid data valid peb 2091 pef 2091 electrical characteristics semiconductor group 276 data sheet 01.99 table 52 iom ? -2 dynamic output characteristics parameter signal symbol limit values unit test condition min. typ. max. data clock rise/fall dcl t r , t f 30 ns c l = 25 pf clock period 1) 1) 256 kbit/s t dcl 1875 1953 2035 ns c l = 25 pf pulse width 1) high/low t wh t wl 850 960 1105 ns clock period 2) 2) 768 kbit/s t dcl 565 651 735 ns c l = 25 pf pulse width 2) high/low t wh t wl 200 310 420 ns frame width high 3) 3) fsc marking superframe fsc t wfh t dcl c l = 25 pf frame width high 4) 4) fsc marking non-superframe fsc t wfh 2 t dcl c l = 25 pf frame synch. rise/fall t r , t f 30 ns c l = 25 pf frame advance t df 065 130ns c l = 25 pf data out dout t f 200 ns c l = 150 pf ( r = 1 k w to v dd , dod pin high) or resq pin low data out t r , t f 150 ns c l = 150 pf dod pin low resq pin high data delay clock 5) 5) the point of time at which the output data will be valid is referred to the rising edges of either fsc ( t ddf ) or dcl ( t ddc ). the rising edge of the signal appearing last (normally dcl) shall be the reference t ddc 100 ns c l = 150 pf data delay frame 5) t ddf 150 ns c l = 150 pf peb 2091 pef 2091 electrical characteristics semiconductor group 277 data sheet 01.99 8.7.4 power controller interface timing note 80: this section is only applicable to the stand-alone mode. note 81: in case the period of signals is stated the time reference will be at 1.4 v; in all other cases 0.8 v (low) and 2.0 v (high) thresholds are used as reference. for pin definition, see "power controller pins", page 36. 8.7.4.1 data port figures 115 and 116 depict the timing for read and write operations. figure 115 dynamic characteristics of power controller write access itd04236 t ddw t sad t wrl pcrd pcwr pca pcd write access 0...1 0...2 . . . peb 2091 pef 2091 electrical characteristics semiconductor group 278 data sheet 01.99 figure 116 dynamic characteristics of power controller read access table 53 power controller interface dynamic characteristics c load = 25pf parameter signal symbol limit values unit min. typ. max. write clock rise/fall pcwr t r, t f 30 ns write with low t wrl 4 t dcl ns address set-up pca0 1 t sad 2 t dcl ns data delay write pcd0 2 t ddw 2 t dcl ns data delay read t ddr 130 ns set-up data read t sdr 130 ns read clock rise/fall pcrd t r, t f 30 ns read width t rdl 4 t dcl ns itd04237 t ddr t sdr t sad t rdl pcrd pcwr pca pcd read access 0...1 0...2 . . . peb 2091 pef 2091 electrical characteristics semiconductor group 279 data sheet 01.99 8.7.4.2 interrupt figure 117 dynamic characteristics of interrupt table 54 dynamic characteristics of interrupt parameter signal symbol limit values unit min. typ. max. interrupt length int t rdl 4 t fsc interrupt width high t wih 0.5 ms interrupt width low t wil 0.5 ms peb 2091 pef 2091 electrical characteristics semiconductor group 280 data sheet 01.99 8.7.5 undervoltage detection timing the timing of the undervoltage detection function is given below. figure 118 uvd timing characteristics table 55 timing parameters of uvd function parameter symbol limit values unit min. typ. max. upper threshold voltage u h 4.1 4.3 4.5 v lower threshold voltage u l u h -0.11 u h -0.085 u h -0.05 v length of reset pulse t r 1) 1) note that this specification holds only if stability of the 15.36 mhz clock is guaranteed. during power-up, the reset pulse may therefor vary slightly from the value mentioned above due to instability of the oscillator during start up 67 ms delay of the reset generation after the threshold voltage has been passed t d 01020 s slope of the rise and fall time of vdd at every point of time dv/dt 0 10 4 v/s u h rst vdd u l t r t d 1.0v t d peb 2091 pef 2091 electrical characteristics semiconductor group 281 data sheet 01.99 8.7.6 master clock 8.7.6.1 lt modes in lt modes (except cot-512/1536 mode) all timing signals are derived from a system clock via an external phase locked loop. the clock specifications for these modes are described below. for the lt modes cot-512 and cot-1536 the requirements as specified in section nt modes on page 283 (nt modes) apply. figure 119 clock requirements in lt modes note 82: fsc*fictitious fsc indicates ideal fsc-clock (existing master clock divided by 1920 without delay). fscreal fsc (contains phase shift resulting from propagation delays in divider). master clock C nominal frequency15.36 mhz C jitter (peak-to-peak) see figure 121, page 282 C max. phase deviation between fsc and fictitious fsc* 18 m s C duty ratio see figure 120, page 282 itd04262 % -frame % clock generation iec-q frame adapt xin 15.36 - mhz master clock system clock dcl fsc fsc* r iom iom r -frame r iom peb 2091 pef 2091 electrical characteristics semiconductor group 282 data sheet 01.99 figure 120 dynamic characteristics of the duty cycle figure 121 maximum sinusoidal input jitter of master clock 15.36 mhz table 56 duty ratio parameter limit values unit min. max. t h 26 39 ns t l 26 39 ns t r , t f 013ns itd04263 t r t hf tt l 10% 90% itd04264 0.08 1.5 57 0.5 19 10k jitter amplitude peak-to-peak ui = unit interval = 65 ns jitter frequency uipp 20 db /decade peb 2091 pef 2091 electrical characteristics semiconductor group 283 data sheet 01.99 8.7.6.2 nt modes this section specifies the requirements of the master clock in all nt and te modes as well as in cot-512/1536 modes. the master clock is derived from a built-in crystal oscillator. the crystal is connected to the pins xin and xout. the maximum capacitive load at xin is 40 pf each. for information about the crystal refer to "oscillator circuit and crystal", page 252. master clock nominal frequency15.36 mhz overall tolerance between lt master clock and nt master clock 100 ppm max. phase deviation between fsc and fictitious fsc* (nt-pbx mode only) : 18 m s nt-pbx mode in nt-pbx mode the iec-q uses an internal data buffer to compensate for phase deviations between iom ? -2-interface and u-interface clocks. this becomes necessary because in nt-pbx mode the device is slave with respect to both interfaces. a phase deviation of up to 18 m s can be compensated by the iec-q. to achieve this a 64 bit wide buffer for user data is implemented in each direction (iom ? -2 ? u and u ? iom ? -2). if the phase deviation becomes too large for the buffer to compensate, the phase relation will be redetermined. this involves the loss of data because a frame jump occurs. each frame jump will be indicated in the c/i channel of the iom ? -2-interface with the indication "fj" (0010 b ). note 83: the "fj" indication will only be issued after a frame jump occurred (independently of the actual phase deviation which led to the frame jump). this indication can therefore not be used as a warning which will be issued when 18 m s phase deviation is reached. peb 2091 pef 2091 electrical characteristics semiconductor group 284 data sheet 01.99 figure 122 clock requirements in nt-pbx 8.7.7 timing properties of cls note 84: in case the period of signals is stated the time reference will be at 1.4 v; in all other cases 0.8 v (low) and 2.0 v (high) thresholds are used as reference. figure 123 dynamic characteristics of cls 1) 1) applies only with a crystal which has the properties given in "oscillator circuit and crystal", page 252 itd04265 frame adapt clock generation % -frame fsc* % % iec-q u dcl fsc u-frame 15.36 - mhz xtal master clock cls 512 khz r iom r iom -frame iom r 0.5 v 2.2 v t r t h t f t l peb 2091 pef 2091 electrical characteristics semiconductor group 285 data sheet 01.99 table 57 output characteristics of cls in nt-rp mode parameter symbol limit values unit test condition min. max. pulse width high, low t h, t l 26 39 ns c load = 20pf rise time, fall time t r, t f 013ns c load = 20pf table 58 output characteristics of cls in nt-pbx and lt-rp modes parameter symbol limit values unit test condition min. max. pulse width high, low t h, t l 850 960 ns c load = 10pf rise time, fall time t r, t f 030ns c load = 10pf table 59 output characteristics of cls in all other modes 1) 1) except lt mode. note that cls is not defined in lt mode parameter symbol limit values unit test condition min. max. pulse width high, low t h, t l 40 90 ns c load = 10pf rise time, fall time t r, t f 025ns c load = 10pf peb 2091 pef 2091 electrical characteristics semiconductor group 286 data sheet 01.99 8.7.8 timing properties of pin sg in te mode c load = 25pf figure 124 dynamic characteristics of pin sg table 60 output characteristics of pin s/g parameter symbol limit values unit min. max. rise time, fall time t r, t f 030ns 0 10 s/g s/g s/g iom ? -2 frame downstream sg pin t r t f peb 2091 pef 2091 package outlines semiconductor group 287 data sheet 01.99 9 package outlines figure 125 package outline for p-lcc-44 plastic package, p-lcc-44 (metric quad flat package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device peb 2091 pef 2091 package outlines semiconductor group 288 data sheet 01.99 figure 126 package outline for m-qfp-64 plastic package, m-qfp-64 (metric quad flat package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device peb 2091 pef 2091 package outlines semiconductor group 289 data sheet 01.99 figure 127 package outline for t-qfp-64 plastic package, t-qfp-64 (thin quad flat package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device peb 2091 pef 2091 glossary semiconductor group 290 data sheet 01.99 10 glossary a/d analog-to digital adc analog-to digital converter agc automatic gain control ain differential u-interface input ansi american national standardization institute arcofi audio ringing codec filter aout differential u-interface output b 64-kbit/s voice and data transmission channel bcl bit clock bin differential u-interface input bout differential u-interface output c/i command/indicate (channel) ccrc corrupted crc crc cyclic redundancy check d 16-kbit/s data and control transmission channel d/a digital-to-analog dac digital-to-analog converter dcl data clock dd data downstream dt data through test mode du data upstream ec echo canceller eoc embedded operations channel eom end of message etsi european telephone standards institute febe far-end block error fifo first-in first-out (memory) fsc frame synchronizing clock gnd ground hdlc high-level data link control icc isdn-communications controller iec-q isdn-echo cancellation circuit conforming to 2b1q-transmission code iom ? -2 isdn-oriented modular 2nd generation info u- and s-interface signal as specified by ansi/etsi isdn integrated services digital network isw inverted synchronization word lb loop back lbbd loop-back of b- and d-channels lsb least significant bit lt line termination mon monitor channel command peb 2091 pef 2091 glossary semiconductor group 291 data sheet 01.99 msb most significant bit mr monitor read bit mto monitor procedure time-out mx monitor transmit bit ncc notify of corrupt crc nebe near-end block error nt network termination osi open systems interconnection pll phase locked loop por power-on reset ps power supply status bit psd power spectral density ptt post, telephone, and telegraph administration pu power-up rcc request corrupt crc rci read power controller interface rms root mean square rp repeater s/t two-wire pair interface sbcx s/t-bus interface circuit extended sicofi signal processing codec filter slic subscriber line interface circuit ssp send single pulses (test mode) st self test sw synchronization word te terminal equipment tl wake-up tone, lt side tn wake-up tone, nt side tp test pin u single wire pair interface utc unable to comply uvd undervoltage detection 2b1q transmission code requiring 80-khz bandwidth peb 2091 pef 2091 index semiconductor group 292 data sheet 01.99 11 index a absolute maximum ratings 262 ac characteristics 269 access to u-interface 106 activation examples 241 in p-nt modes 298 in nt-auto activation mode 142 in the p-nt mode 142 initiated by lt 126 initiated by lt with repeater 135 initiated by lt with u active 131 initiated by te 128 initiated by te with repeater 136 initiated by te with u active 132 partial 130 with act-bit status ignored 127 adc 65 analog characteristics 266 ansi 297 application hints 248 b bac bit 198 basic standards 297 bellcore 297 block diagram 58 analog loop-back function 66 analog-to-digital converter 65 awake block 65 clocks 83 control block 64 digital-to-analog converter 65 eoc processor 64 in p mode 58 in stand alone mode 59 line driver 66 line interface unit 65 microprocessor interface 90 microprocessor mode 58 power controller interface 91 power status 92 receiver 65 s/g bit and bac bit control 90 single bits processor 64 special functions 64 system interface unit 62 test block 95 transceiver core 60 transmitter buffer 62 u transceiver 61 u-interface 67 undervoltage detection 92 block error counters 178 febe 179 nebe 178 test overview 183 testing 180 bt 297 c c/i channel 75 abbreviation 225 codes 224 programming example 232 c/i channel example 232 chip identification 193 clock generation 83 cot mode 88 lt repeater 88 lt-mode 84 microprocessor clock output 89 nt- and te-mode 85 nt-pbx 86 repeater modes 87 clocks cls timing 284 duty cycle 282 jitter of master clock 282 pin sg timing 286 timing 281 cold start 146 cot application 23 peb 2091 pef 2091 index semiconductor group 293 data sheet 01.99 cyclic redundancy check 64 violation indications 184 d dac 65 output for a single pulse 66 dc characteristics 268 deactivation complete 129 examples 241 loss of synchronization at rp 137 s/t-interface only 134 with repeater 141 dout driver modes 53 e electrical characteristics 262 elic example for pbx application 253 eoc 231 codes 231 etsi 297 external circuitry 249 hybrid 250 oscillator circuit 252 power supply blocking 249 f features 19 functional description 49 g glossary 290 h hybrid 250 i identification 193 iec afe/dfe-q 18 iom ? -2 act./deact. of clocks 82 active 55 active c/i channel 75 active channel 72 active monitor channel 76 basic channel structure 71 bit clock mode 56 c/i channel 1 76 c/i channels 75 commands 75 dynamic input characteristics 275 dynamic output characteristics 276 enable/disable mode 53 frame structure 70 idle 54 indications 75 interface 70 interface timing 274 master mode 70 monitor channel 76 monitor channel structure 76 multiplexed frame structure 72 multiplexed timing mode 71 passive channels 72 plain frame structure 73 plain timing mode 72 setting enable/disable mode 55 slave mode 70 terminal frame structure 74 itu 297 l line interface unit 65 line overload protection 264 logic symbol 21 p mode 21 stand alone mode 22 lt application 29 m master mode 70 microprocessor bus selection 90 microprocessor interface 48 b1/b2-channel data registers 98 b-channel access 98 peb 2091 pef 2091 index semiconductor group 294 data sheet 01.99 c/i channel access 100 d-channel access 99 d-channel data registers 99 d-channel processing 99 interrupt structure 209 modes 90 monitor channel access 101 monitor channel protocol 103, 104 monitor receive bits 103 monitor transmit bits 103 microprocessor timing 269 motorola bus mode 271 serial mode 273 siemens/intel bus mode 270 values in parallel mode 272 values in serial mode 274 modes 50 basic setting 50 dout driver 54 iom ? -2 channel assignment 52 setting dout driver 53, 54 setting eoc mode 56 setting iom ? -2 bit clock 56 setting iom ? -2 clock 55 setting mto mode 56 setting test modes 52 monitor channel 76 codes 226 interrupt 209 mon-0 codes 226 mon-1 codes 227 mon-2 codes 228 mon-8 codes 228 programming example 233 monitor channel 76 access with mto enabled 81 channel 1 80 handshake procedure 77 handshake protocol 78 idle state 78 priority 77 structure 76 time-out 80 transmission abortion 78 verification 77 m-qfp-64 ordering code 20 package outline 288 pin configuration 32 n nt1 application 30 ntc-q and intc-q 18 nt-pbx application 28 o operating modes 92 operational description 96 ordering codes 20 oscillator circuit 252 overview 18 p package outlines 287 pcm 4 application 24 pins 31 p control 42 p interface 40 capacitances 269 clocks 45 in microprocessor mode 40 iom ? -2 35, 44 iom ? -2 control 35 microprocessor bus interface 48 miscellaneous function 39, 46 mode selection 33, 40 pin configuration 31 pin definitions 32 p-lcc-44 pin configuration 31 power controller 36, 45 power supply 34, 43 test 39, 47 u-interface 36, 44 p-lcc-44 ordering code 20 package outline 287 peb 2091 pef 2091 index semiconductor group 295 data sheet 01.99 pin configuration 31 power consumption 265 power controller interface 91, 196 access 196 data port 196 data port timing 277 interrupt 197 interrupt timing 279 programming example 235 timing 277 power status pin access 194 power status pins 194 diss 195 ps1 194 ps2 194 power supply 263 preface 16 programming 223 c/i channel codes 224 r receiver 65 registers 206 address map 207 adf2-register 214 adf-register 219 b-channel access 221 ciri-register 218 ciru-register 217 ciwi-register 218 ciwu-register 217 d-channel access 221 ista-register 210 mask-register 211 mocr-register 216 monitor-channel access 222 mosr-register 215 stcr-register 212 summary 208 swst-register 220 repeater 143 hints for applications 257 wake-up indication 143 repeater application 25 reset 94 reset behavior definition 94 sources 95 rt application 23 s s/g bit 198 state machine 200 status on pin sg 205 sigma-delta modulator 65 single bits 115 slave mode 70 standards 297 state diagram 161 state machine notation rules 145 state machines 145 in nt-modes 160 in repeater modes 173 lt-repeater diagram 174 notation 145 notation rules 145 nt states 168 nt-auto activation 162 nt-modes state diagram 161 nt-repeater diagram 175 timers for nt 167 superframe marker 124 enable in p mode 124 setting 124 system integration 23 access networ 28 lt application 29 nt1 30 nt-pbx 28 pcm 2 systems 23 pcm 4 24 repeater 24 te applications 26 wireless local loop 25 system interface unit 62 peb 2091 pef 2091 index semiconductor group 296 data sheet 01.99 system measurements 259 insertion loss 260 power spectral-density 260 pulse mask 259 quiet mode 261 return-loss 261 total power 260 t te application 26 test modes 53 test options 185 analog loop-back 187 chip internal 185 codes 191 complete loop-back 189 examples 236 loop-backs 186 receiver coefficient values 185 repeater loop-back 190 self-test 185 single-channel loop-backs 190 t-qfp-64 ordering code 20 package outline 289 pin configuration 32 u u-interface 67 access to data channels 108 access to eoc 110 access to the single bits 115 basic frame structure 67 channels of access 106 eoc-procedure 114 frame structure 67, 68 output and input signals 67 signals 125 single bits reception 120 single bits transmission 115 u-interface hybrid 250 u-interface signals 125 uvd 93 timing 280 w warm start 146 peb 2091 pef 2091 semiconductor group 297 data sheet 01.99 appendix a basic standards the following table gives a list of the most important standards related to the iec-q. organization valid for document itu international telecommunication union world- wide itu-t g.961 digital transmission system on metallic line for isdn basic rate access etsi european telecommunications standards institute eu "etsi technical report 080" (etr080), nov. 1996 new name (1999) "technical specification 101080" (ts 101080) transmission and multiplexing; isdn basic rate access; digital transmission systems on metallic local lines ansi american national standards institute, inc. usa t1e1 4/92-004 - t1.601-1992 basic access interface for use on metallic loops for application on the network side of the nt (layer 1 specification) bellcore usa tr-nwt-000393, issue 2, december 1992 generic requirements for isdn basic access digital subscriber lines tr-nwt-000397, issue 3, december 1993 isdn basic access transport system requirements tr-nwt-000829, issue 1, november 1989 otgr: generic operations interface, embedded operations channel sr-nwt-002397, issue 1, june 1993 layer 1 test plan for isdn basic access digital subscriber line transceivers bt british telecommunications plc. gb specification rc7355e, issue e, 03/97 2b1q generic physical layer specification peb 2091 pef 2091 semiconductor group 298 data sheet 01.99 appendix b comment on activation in p-nt modes erroneous signals on u-interface after power-up in nt mode with enabled microprocessor interface mode this point applies only if the iec-q is used in nt mode and if the microprocessor interface mode is enabled by pin pmode set to "1". the stand-alone mode is not affected. after applying v dd (power-on) the device enters the lt mode according to the default value c4 h in the stcr register (see "stcr-register", page 212). in applications where no iom ? -2 clocks are provided to the peb/f 2091 version 5.1 this results in an undefined state of the iec-q. the undefined state may cause unwanted signals on the u-interface. it is left once the device is brought into the nt or te mode by programming the stcr register. thus, for the time between applying v dd and programming the stcr register, unwanted signals may be sent on the u-interface. in the psb/f 21911 iec-q te the default value of the stcr register has been changed to "04h". thus "unwanted" signals wont be sent on the u-interface any longer. |
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